Show patches with: Submitter = Anup Patel       |    State = Action Required       |    Archived = No       |   177 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[1/2] hw/riscv: sifive_u: Allow passing custom DTB [1/2] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-22 Anup Patel New
[1/2] hw: timer: Add Goldfish RTC device RTC support for QEMU RISC-V virt machine - - - - --- 2019-09-24 Anup Patel New
[1/2] target/riscv: Emulate TIME CSRs for privileged mode RISC-V TIME CSR for privileged mode - - 1 - --- 2020-01-21 Anup Patel New
[1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() RISC-V Spike machine improvements - - 1 - --- 2020-02-14 Anup Patel New
[1/3] target/riscv: Optional feature to provide trapped instruction in CSRs Trapped instruction encoding support - - 1 - --- 2020-07-29 Anup Patel New
[1/4] hw/riscv: Allow creating multiple instances of CLINT RISC-V multi-socket support - - 2 - --- 2020-05-16 Anup Patel New
[1/4] target/riscv: Add defines for AIA local interrupt CSRs AIA local interrupt CSR support - - 1 - --- 2021-05-14 Anup Patel New
[2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation RISC-V TIME CSR for privileged mode - - 1 - --- 2020-01-21 Anup Patel New
[2/2] hw/riscv: virt: Allow passing custom DTB [1/2] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-22 Anup Patel New
[2/2] riscv: virt: Use Goldfish RTC device RTC support for QEMU RISC-V virt machine - - - - --- 2019-09-24 Anup Patel New
[2/3] hw/riscv/spike: Allow loading firmware separately using -bios option RISC-V Spike machine improvements - - 1 - --- 2020-02-14 Anup Patel New
[2/3] target/riscv: Fix write_htinst() implementation Trapped instruction encoding support - - 1 - --- 2020-07-29 Anup Patel New
[2/4] hw/riscv: spike: Allow creating multiple sockets RISC-V multi-socket support - - - - --- 2020-05-16 Anup Patel New
[2/4] target/riscv: Add CPU feature for AIA CSRs AIA local interrupt CSR support - - - - --- 2021-05-14 Anup Patel New
[3/3] hw/riscv/spike: Allow more than one CPUs RISC-V Spike machine improvements - - 1 - --- 2020-02-14 Anup Patel New
[3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() Trapped instruction encoding support - - - - --- 2020-07-29 Anup Patel New
[3/4] hw/riscv: Allow creating multiple instances of PLIC RISC-V multi-socket support - - 2 - --- 2020-05-16 Anup Patel New
[3/4] target/riscv: Implement AIA local interrupt CSRs AIA local interrupt CSR support - - - - --- 2021-05-14 Anup Patel New
[4/4] hw/riscv: virt: Allow creating multiple sockets RISC-V multi-socket support - - - - --- 2020-05-16 Anup Patel New
[4/4] hw/riscv: virt: Use AIA INTC compatible string when available AIA local interrupt CSR support - - 1 - --- 2021-05-14 Anup Patel New
[v1,1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT RISC-V ACLINT Support - - - - --- 2021-06-12 Anup Patel New
[v1,2/3] hw/riscv: virt: Re-factor FDT generation RISC-V ACLINT Support - - - - --- 2021-06-12 Anup Patel New
[v1,3/3] hw/riscv: virt: Add optional ACLINT support to virt machine RISC-V ACLINT Support - - - - --- 2021-06-12 Anup Patel New
[v2,01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode QEMU RISC-V AIA support - 1 1 - --- 2021-09-02 Anup Patel New
[v2,02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs QEMU RISC-V AIA support - - 1 - --- 2021-09-02 Anup Patel New
[v2,03/22] target/riscv: Implement hgeie and hgeip CSRs QEMU RISC-V AIA support - - 1 - --- 2021-09-02 Anup Patel New
[v2,04/22] target/riscv: Improve fidelity of guest external interrupts QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,05/22] target/riscv: Allow setting CPU feature from machine/device emulation QEMU RISC-V AIA support - - 2 - --- 2021-09-02 Anup Patel New
[v2,06/22] target/riscv: Add AIA cpu feature QEMU RISC-V AIA support - - 2 - --- 2021-09-02 Anup Patel New
[v2,07/22] target/riscv: Add defines for AIA CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,1/2] hw: timer: Add Goldfish RTC device RTC support for QEMU RISC-V virt machine - - - - --- 2019-09-24 Anup Patel New
[v2,1/2] target/riscv: Emulate TIME CSRs for privileged mode RISC-V TIME CSR for privileged mode - - 1 - --- 2020-01-22 Anup Patel New
[v2,1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() RISC-V Spike machine improvements - - - - --- 2020-03-03 Anup Patel New
[v2,1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources QEMU RISC-V ACLINT Support - - 2 - --- 2021-07-24 Anup Patel New
[v2,1/5] hw: Add sockets_specified field in CpuTopology RISC-V multi-socket support - - - - --- 2020-05-27 Anup Patel New
[v2,10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,12/22] target/riscv: Implement AIA interrupt filtering CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,14/22] target/riscv: Implement AIA xiselect and xireg CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,15/22] target/riscv: Implement AIA IMSIC interface CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,16/22] hw/riscv: virt: Use AIA INTC compatible string when available QEMU RISC-V AIA support - - 1 - --- 2021-09-02 Anup Patel New
[v2,17/22] target/riscv: Allow users to force enable AIA CSRs in HART QEMU RISC-V AIA support - - 1 - --- 2021-09-02 Anup Patel New
[v2,18/22] hw/intc: Add RISC-V AIA APLIC device emulation QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation RISC-V TIME CSR for privileged mode - - 1 - --- 2020-01-22 Anup Patel New
[v2,2/2] riscv: virt: Use Goldfish RTC device RTC support for QEMU RISC-V virt machine - - - - --- 2019-09-24 Anup Patel New
[v2,2/3] hw/riscv/spike: Allow loading firmware separately using -bios option RISC-V Spike machine improvements - - - - --- 2020-03-03 Anup Patel New
[v2,2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT QEMU RISC-V ACLINT Support - - - - --- 2021-07-24 Anup Patel New
[v2,2/5] hw/riscv: Allow creating multiple instances of CLINT RISC-V multi-socket support - - 2 - --- 2020-05-27 Anup Patel New
[v2,20/22] hw/intc: Add RISC-V AIA IMSIC device emulation QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,22/22] docs/system: riscv: Document AIA options for virt machine QEMU RISC-V AIA support - - 1 - --- 2021-09-02 Anup Patel New
[v2,3/3] hw/riscv/spike: Allow more than one CPUs RISC-V Spike machine improvements - - - - --- 2020-03-03 Anup Patel New
[v2,3/4] hw/riscv: virt: Re-factor FDT generation QEMU RISC-V ACLINT Support - - 2 - --- 2021-07-24 Anup Patel New
[v2,3/5] hw/riscv: spike: Allow creating multiple sockets RISC-V multi-socket support - - - - --- 2020-05-27 Anup Patel New
[v2,4/4] hw/riscv: virt: Add optional ACLINT support to virt machine QEMU RISC-V ACLINT Support - - 2 - --- 2021-07-24 Anup Patel New
[v2,4/5] hw/riscv: Allow creating multiple instances of PLIC RISC-V multi-socket support - - 2 - --- 2020-05-27 Anup Patel New
[v2,5/5] hw/riscv: virt: Allow creating multiple sockets RISC-V multi-socket support - - - - --- 2020-05-27 Anup Patel New
[v2] riscv/virt: Add syscon reboot and poweroff DT nodes [v2] riscv/virt: Add syscon reboot and poweroff DT nodes - - 2 - --- 2020-01-22 Anup Patel New
[v3,01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode QEMU RISC-V AIA support - 1 1 - --- 2021-10-23 Anup Patel New
[v3,02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,03/22] target/riscv: Implement hgeie and hgeip CSRs QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,04/22] target/riscv: Improve delivery of guest external interrupts QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,05/22] target/riscv: Allow setting CPU feature from machine/device emulation QEMU RISC-V AIA support - - 2 - --- 2021-10-23 Anup Patel New
[v3,06/22] target/riscv: Add AIA cpu feature QEMU RISC-V AIA support - - 2 - --- 2021-10-23 Anup Patel New
[v3,07/22] target/riscv: Add defines for AIA CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,09/22] target/riscv: Implement AIA local interrupt priorities QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,1/2] hw: timer: Add Goldfish RTC device RTC support for QEMU RISC-V virt machine - - - - --- 2019-10-15 Anup Patel New
[v3,1/2] target/riscv: Emulate TIME CSRs for privileged mode RISC-V TIME CSR for privileged mode - - 1 - --- 2020-02-02 Anup Patel New
[v3,1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() RISC-V Spike machine improvements - - 1 - --- 2020-04-27 Anup Patel New
[v3,1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources QEMU RISC-V ACLINT Support - - 2 - --- 2021-08-29 Anup Patel New
[v3,1/4] hw/riscv: Allow creating multiple instances of CLINT RISC-V multi-socket support - - 2 - --- 2020-05-27 Anup Patel New
[v3,10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,12/22] target/riscv: Implement AIA interrupt filtering CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,14/22] target/riscv: Implement AIA xiselect and xireg CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,15/22] target/riscv: Implement AIA IMSIC interface CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,16/22] hw/riscv: virt: Use AIA INTC compatible string when available QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,17/22] target/riscv: Allow users to force enable AIA CSRs in HART QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,18/22] hw/intc: Add RISC-V AIA APLIC device emulation QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation RISC-V TIME CSR for privileged mode - - 1 - --- 2020-02-02 Anup Patel New
[v3,2/2] riscv: virt: Use Goldfish RTC device RTC support for QEMU RISC-V virt machine 1 - 2 - --- 2019-10-15 Anup Patel New
[v3,2/3] hw/riscv/spike: Allow loading firmware separately using -bios option RISC-V Spike machine improvements - - 1 - --- 2020-04-27 Anup Patel New
[v3,2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT QEMU RISC-V ACLINT Support - - 1 - --- 2021-08-29 Anup Patel New
[v3,2/4] hw/riscv: spike: Allow creating multiple sockets RISC-V multi-socket support - - - - --- 2020-05-27 Anup Patel New
[v3,20/22] hw/intc: Add RISC-V AIA IMSIC device emulation QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,22/22] docs/system: riscv: Document AIA options for virt machine QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,3/3] hw/riscv/spike: Allow more than one CPUs RISC-V Spike machine improvements - - 1 - --- 2020-04-27 Anup Patel New
[v3,3/4] hw/riscv: Allow creating multiple instances of PLIC RISC-V multi-socket support - - 2 - --- 2020-05-27 Anup Patel New
[v3,3/4] hw/riscv: virt: Re-factor FDT generation QEMU RISC-V ACLINT Support - - 2 - --- 2021-08-29 Anup Patel New
[v3,4/4] hw/riscv: virt: Add optional ACLINT support to virt machine QEMU RISC-V ACLINT Support - - 2 - --- 2021-08-29 Anup Patel New
[v3,4/4] hw/riscv: virt: Allow creating multiple sockets RISC-V multi-socket support - - 1 - --- 2020-05-27 Anup Patel New
[v4,01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode QEMU RISC-V AIA support - 1 2 - --- 2021-10-26 Anup Patel New
[v4,02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs QEMU RISC-V AIA support - - 1 - --- 2021-10-26 Anup Patel New
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