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Alistair Francis
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Apply
«
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[1/2] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled
RISC-V: OpenTitan: Fixup ePMP and SPI interrupts
- - 1 -
-
-
-
2023-11-02
Alistair Francis
New
[1/3] hw/pci: Add all Data Object Types
[1/3] hw/pci: Add all Data Object Types
- - - -
-
-
-
2023-09-15
Alistair Francis
New
[1/3] target/riscv: Assert that the CSR numbers will be correct
target/riscv: A few bug fixes and Coverity fix
- 1 1 -
-
-
-
2024-01-08
Alistair Francis
New
[1/4] hw/riscv: opentitan: Fixup local variables shadowing
RISC-V: Work towards enabling -Wshadow=local
- - 1 -
-
-
-
2023-09-25
Alistair Francis
New
[2/2] target/riscv: cpu: Set the OpenTitan priv to 1.12.0
RISC-V: OpenTitan: Fixup ePMP and SPI interrupts
- - 1 -
-
-
-
2023-11-02
Alistair Francis
New
[2/3] backends: Initial support for SPDM socket support
[1/3] hw/pci: Add all Data Object Types
- - - -
-
-
-
2023-09-15
Alistair Francis
New
[2/3] target/riscv: Don't adjust vscause for exceptions
target/riscv: A few bug fixes and Coverity fix
- - 1 -
-
-
-
2024-01-08
Alistair Francis
New
[2/4] target/riscv: cpu: Fixup local variables shadowing
RISC-V: Work towards enabling -Wshadow=local
- - 1 -
-
-
-
2023-09-25
Alistair Francis
New
[3/3] hw/nvme: Add SPDM over DOE support
[1/3] hw/pci: Add all Data Object Types
- - - -
-
-
-
2023-09-15
Alistair Francis
New
[3/3] target/riscv: Ensure mideleg is set correctly on reset
target/riscv: A few bug fixes and Coverity fix
- - 1 -
-
-
-
2024-01-08
Alistair Francis
New
[3/4] target/riscv: vector_helper: Fixup local variables shadowing
RISC-V: Work towards enabling -Wshadow=local
- - 1 -
-
-
-
2023-09-25
Alistair Francis
New
[4/4] softmmu/device_tree: Fixup local variables shadowing
RISC-V: Work towards enabling -Wshadow=local
- - 1 -
-
-
-
2023-09-25
Alistair Francis
New
[Bug,1630723,NEW] UART writes to netduino2/stm32f205-soc disappear
- - - -
-
-
-
2016-10-25
Alistair Francis
New
[Bug,1630723,NEW] UART writes to netduino2/stm32f205-soc disappear
- - - -
-
-
-
2016-10-07
Alistair Francis
New
[PULL,0/1] riscv-to-apply queue
- - - -
-
-
-
2023-07-23
Alistair Francis
New
[PULL,0/2] riscv-to-apply queue
- - - -
-
-
-
2023-08-11
Alistair Francis
New
[PULL,0/5] riscv-to-apply queue
- - - -
-
-
-
2023-07-19
Alistair Francis
New
[PULL,0/6] riscv-to-apply queue
- - - -
-
-
-
2023-11-22
Alistair Francis
New
[PULL,00/15] riscv-to-apply queue
- - - -
-
-
-
2024-03-22
Alistair Francis
New
[PULL,00/34] riscv-to-apply queue
- - - -
-
-
-
2024-03-08
Alistair Francis
New
[PULL,00/49] riscv-to-apply queue
- - - -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,00/54] riscv-to-apply queue
- - - -
-
-
-
2023-10-12
Alistair Francis
New
[PULL,00/54] riscv-to-apply queue
- - - -
-
-
-
2023-07-10
Alistair Francis
New
[PULL,00/60] riscv-to-apply queue
- - - -
-
-
-
2023-06-14
Alistair Francis
New
[PULL,00/61] riscv-to-apply queue
- - - -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,00/65] riscv-to-apply queue
- - - -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,00/65] riscv-to-apply queue
- - - -
-
-
-
2023-09-08
Alistair Francis
New
[PULL,00/89] riscv-to-apply queue
- - - -
-
-
-
2023-05-05
Alistair Francis
New
[PULL,01/15] target/riscv: do not enable all named features by default
[PULL,01/15] target/riscv: do not enable all named features by default
- 1 2 1
-
-
-
2024-03-22
Alistair Francis
New
[PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
[PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
- - 2 -
-
-
-
2024-03-08
Alistair Francis
New
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 2 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
[PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
- - 3 -
-
-
-
2023-10-12
Alistair Francis
New
[PULL,01/54] target/riscv: Use xl instead of mxl for disassemble
[PULL,01/54] target/riscv: Use xl instead of mxl for disassemble
- - 2 -
-
-
-
2023-07-10
Alistair Francis
New
[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero
[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero
1 - 2 -
-
-
-
2023-06-14
Alistair Francis
New
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- - 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG
- - 2 -
-
-
-
2023-09-08
Alistair Francis
New
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
- - 2 -
-
-
-
2023-05-05
Alistair Francis
New
[PULL,02/15] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
[PULL,01/15] target/riscv: do not enable all named features by default
- - 3 -
-
-
-
2024-03-22
Alistair Francis
New
[PULL,02/34] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
[PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
- - 1 -
-
-
-
2024-03-08
Alistair Francis
New
[PULL,02/49] target/riscv: rename ext_icsr to ext_zicsr
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 2 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,02/54] target/riscv/cpu.c: skip 'bool' check when filtering KVM props
[PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
- - 2 -
-
-
-
2023-10-12
Alistair Francis
New
[PULL,02/54] target/riscv: Factor out extension tests to cpu_cfg.h
[PULL,01/54] target/riscv: Use xl instead of mxl for disassemble
- - 3 -
-
-
-
2023-07-10
Alistair Francis
New
[PULL,02/60] target/riscv: Move zc* out of the experimental properties
[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero
- - 2 -
-
-
-
2023-06-14
Alistair Francis
New
[PULL,02/61] target/riscv: Add infrastructure for 'B' MISA extension
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- - 3 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,02/65] hw/char/riscv_htif: Fix printing of console characters on big endian hosts
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG
- 1 4 -
-
-
-
2023-09-08
Alistair Francis
New
[PULL,02/65] target/riscv: The whole vector register move instructions depend on vsew
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
1 - - -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,02/89] target/riscv: Fix priv version dependency for vector and zfh
[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
- - 2 -
-
-
-
2023-05-05
Alistair Francis
New
[PULL,03/15] trans_rvv.c.inc: set vstart = 0 in int scalar move insns
[PULL,01/15] target/riscv: do not enable all named features by default
- 1 2 -
-
-
-
2024-03-22
Alistair Francis
New
[PULL,03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table
[PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
- - 1 -
-
-
-
2024-03-08
Alistair Francis
New
[PULL,03/49] target/riscv: rename ext_icbom to ext_zicbom
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 2 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,03/54] disas/riscv: Move types/constants to new header file
[PULL,01/54] target/riscv: Use xl instead of mxl for disassemble
- - 2 -
-
-
-
2023-07-10
Alistair Francis
New
[PULL,03/54] target/riscv/cpu.c: split kvm prop handling to its own helper
[PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
- - 1 -
-
-
-
2023-10-12
Alistair Francis
New
[PULL,03/60] target/riscv/cpu.c: add riscv_cpu_validate_v()
[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero
- - 3 -
-
-
-
2023-06-14
Alistair Francis
New
[PULL,03/61] target/riscv: Add step to validate 'B' extension
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- - 3 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,03/65] hw/char/riscv_htif: Fix the console syscall on big endian hosts
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG
- 1 3 -
-
-
-
2023-09-08
Alistair Francis
New
[PULL,03/65] target/riscv: Fix th.dcache.cval1 priviledge check
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,03/89] target/riscv: Simplify getting RISCVCPU pointer from env
[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
- - 3 -
-
-
-
2023-05-05
Alistair Francis
New
[PULL,04/15] target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
[PULL,01/15] target/riscv: do not enable all named features by default
- 1 3 -
-
-
-
2024-03-22
Alistair Francis
New
[PULL,04/34] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM
[PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
- - 2 -
-
-
-
2024-03-08
Alistair Francis
New
[PULL,04/49] target/riscv: rename ext_icboz to ext_zicboz
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 2 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,04/54] disas/riscv: Make rv_op_illegal a shared enum value
[PULL,01/54] target/riscv: Use xl instead of mxl for disassemble
- - 2 -
-
-
-
2023-07-10
Alistair Francis
New
[PULL,04/54] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
[PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
- - 3 -
-
-
-
2023-10-12
Alistair Francis
New
[PULL,04/60] target/riscv/cpu.c: remove set_vext_version()
[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero
- - 3 -
-
-
-
2023-06-14
Alistair Francis
New
[PULL,04/61] target/riscv/cpu_cfg.h: remove unused fields
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- - 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,04/65] target/riscv/cpu.c: add zmmul isa string
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG
- 1 2 -
-
-
-
2023-09-08
Alistair Francis
New
[PULL,04/65] target/riscv: Not allow write mstatus_vs without RVV
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,04/89] target/riscv: Simplify type conversion for CPURISCVState
[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
- - 2 -
-
-
-
2023-05-05
Alistair Francis
New
[PULL,05/15] target/riscv: always clear vstart in whole vec move insns
[PULL,01/15] target/riscv: do not enable all named features by default
- 1 3 -
-
-
-
2024-03-22
Alistair Francis
New
[PULL,05/34] linux-user/riscv: Add Zicboz extensions to hwprobe
[PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
- - 1 -
-
-
-
2024-03-08
Alistair Francis
New
[PULL,05/49] target/riscv: Without H-mode mask all HS mode inturrupts in mie.
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,05/54] disas/riscv: Encapsulate opcode_data into decode
[PULL,01/54] target/riscv: Use xl instead of mxl for disassemble
- - 1 -
-
-
-
2023-07-10
Alistair Francis
New
[PULL,05/54] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
[PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
- - 2 -
-
-
-
2023-10-12
Alistair Francis
New
[PULL,05/60] target/riscv/cpu.c: remove set_priv_version()
[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero
- - 3 -
-
-
-
2023-06-14
Alistair Francis
New
[PULL,05/61] target/riscv: make riscv_cpu_is_vendor() public
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- - 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,05/65] target/riscv/cpu.c: add smepmp isa string
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG
- - 2 -
-
-
-
2023-09-08
Alistair Francis
New
[PULL,05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,05/89] target/riscv: Simplify arguments for riscv_csrrw_check
[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
- - 3 -
-
-
-
2023-05-05
Alistair Francis
New
[PULL,06/15] target/riscv: always clear vstart for ldst_whole insns
[PULL,01/15] target/riscv: do not enable all named features by default
- 1 2 -
-
-
-
2024-03-22
Alistair Francis
New
[PULL,06/34] linux-user/riscv: Sync hwprobe keys with Linux
[PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
- - 1 -
-
-
-
2024-03-08
Alistair Francis
New
[PULL,06/49] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,06/54] disas/riscv: Provide infrastructure for vendor extensions
[PULL,01/54] target/riscv: Use xl instead of mxl for disassemble
- - 2 -
-
-
-
2023-07-10
Alistair Francis
New
[PULL,06/54] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
[PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
- - 2 -
-
-
-
2023-10-12
Alistair Francis
New
[PULL,06/60] target/riscv: add PRIV_VERSION_LATEST
[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero
- - 4 -
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-
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2023-06-14
Alistair Francis
New
[PULL,06/61] target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- - 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,06/65] target/riscv/cpu.c: fix machine IDs getters
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- 3 2 -
-
-
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2024-01-10
Alistair Francis
New
[PULL,06/65] target/riscv: Fix page_check_range use in fault-only-first
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG
- - 1 -
-
-
-
2023-09-08
Alistair Francis
New
[PULL,06/89] target/riscv: refactor Zicond support
[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
1 - 1 -
-
-
-
2023-05-05
Alistair Francis
New
[PULL,07/15] target/riscv/vector_helpers: do early exit when vstart >= vl
[PULL,01/15] target/riscv: do not enable all named features by default
1 - 1 -
-
-
-
2024-03-22
Alistair Francis
New
[PULL,07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
[PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
- - 1 -
-
-
-
2024-03-08
Alistair Francis
New
[PULL,07/49] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,07/54] disas/riscv: Add support for XVentanaCondOps
[PULL,01/54] target/riscv: Use xl instead of mxl for disassemble
1 - 1 -
-
-
-
2023-07-10
Alistair Francis
New
[PULL,07/54] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
[PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
- - 3 -
-
-
-
2023-10-12
Alistair Francis
New
[PULL,07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv versi…
[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero
1 - 1 -
-
-
-
2023-06-14
Alistair Francis
New
[PULL,07/61] target/riscv: move 'mmu' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- - 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,07/65] target/riscv: Use existing lookup tables for MixColumns
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG
- - 1 -
-
-
-
2023-09-08
Alistair Francis
New
[PULL,07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions
[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
1 - 1 -
-
-
-
2023-05-05
Alistair Francis
New
[PULL,08/15] target/riscv: remove 'over' brconds from vector trans
[PULL,01/15] target/riscv: do not enable all named features by default
- - 2 -
-
-
-
2024-03-22
Alistair Francis
New
[PULL,08/34] target/riscv: add riscv,isa to named features
[PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
- - 2 -
-
-
-
2024-03-08
Alistair Francis
New
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