Show patches with: Submitter = Bastian Koppelmann       |    State = Action Required       |    Archived = No       |   975 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[01/10] target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3 - - 1 - --- 2015-05-13 Bastian Koppelmann New
[01/10] tests/tcg/tricore: Bump cpu to tc37x TriCore 1.6.2 insn and bugfixes 1 - - - --- 2023-08-26 Bastian Koppelmann New
[01/10] tests/tcg/tricore: Extended and non-extened regs now match TriCore tests and cleanups - - - - --- 2023-09-13 Bastian Koppelmann New
[01/15] target-tricore: Add target stubs and qom-cpu - - - - --- 2014-07-07 Bastian Koppelmann New
[01/28] targer/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[02/10] hw/tricore: Log failing test in testdevice TriCore tests and cleanups - - - - --- 2023-09-13 Bastian Koppelmann New
[02/10] target-tricore: introduce ISA v1.6.1 feature - - 1 - --- 2015-05-13 Bastian Koppelmann New
[02/10] target/tricore: Implement CRCN insn TriCore 1.6.2 insn and bugfixes - - - - --- 2023-08-26 Bastian Koppelmann New
[02/15] target-tricore: Add board for systemmode - - - - --- 2014-07-07 Bastian Koppelmann New
[02/28] target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert to decodetree - - - - --- 2018-10-12 Bastian Koppelmann New
[03/10] target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA - - 1 - --- 2015-05-13 Bastian Koppelmann New
[03/10] target/tricore: Correctly handle FPU RM from PSW TriCore 1.6.2 insn and bugfixes - - 1 - --- 2023-08-26 Bastian Koppelmann New
[03/10] tests/tcg: Reset result register after each test TriCore tests and cleanups - - - - --- 2023-09-13 Bastian Koppelmann New
[03/15] target-tricore: Add softmmu support - - - - --- 2014-07-07 Bastian Koppelmann New
[03/28] target/riscv: Convert RVXI load/store insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[04/10] target-tricore: add CMPSWP instructions of the v1.6.1 ISA - - 1 - --- 2015-05-13 Bastian Koppelmann New
[04/10] target/tricore: Implement FTOU insn TriCore 1.6.2 insn and bugfixes - - - - --- 2023-08-26 Bastian Koppelmann New
[04/10] tests/tcg/tricore: Add test for all arith insns up to addx TriCore tests and cleanups - - - - --- 2023-09-13 Bastian Koppelmann New
[04/15] target-tricore: Add initialization for translation - - - - --- 2014-07-07 Bastian Koppelmann New
[04/28] target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert to decodetree - - - - --- 2018-10-12 Bastian Koppelmann New
[05/10] target-tricore: add SWAPMSK instructions of the v1.6.1 ISA - - 1 - --- 2015-05-13 Bastian Koppelmann New
[05/10] target/tricore: Implement ftohp insn TriCore 1.6.2 insn and bugfixes - - - - --- 2023-08-26 Bastian Koppelmann New
[05/10] tests/tcg/tricore: Add test for and to csub TriCore tests and cleanups - - - - --- 2023-09-13 Bastian Koppelmann New
[05/15] target-tricore: Add masks and opcodes for decoding - - - - --- 2014-07-07 Bastian Koppelmann New
[05/28] target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert to decodetree - - - - --- 2018-10-12 Bastian Koppelmann New
[06/10] target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA - - 1 - --- 2015-05-13 Bastian Koppelmann New
[06/10] target/tricore: Implement hptof insn TriCore 1.6.2 insn and bugfixes - - - - --- 2023-08-26 Bastian Koppelmann New
[06/10] tests/tcg/tricore: Add from dextr to lt TriCore tests and cleanups - - - - --- 2023-09-13 Bastian Koppelmann New
[06/15] target-tricore: Add instructions of SRC opcode format - - - - --- 2014-07-07 Bastian Koppelmann New
[06/28] target/riscv: Convert RVXI csr insns to decodetree Untitled series #70547 - - 1 - --- 2018-10-12 Bastian Koppelmann New
[07/10] target-tricore: add SYS_RESTORE instruction of the v1.6 ISA - - 1 - --- 2015-05-13 Bastian Koppelmann New
[07/10] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 TriCore 1.6.2 insn and bugfixes - - 1 - --- 2023-08-26 Bastian Koppelmann New
[07/10] tests/tcg/tricore: Add test from 'max' to 'shas' TriCore tests and cleanups - - - - --- 2023-09-13 Bastian Koppelmann New
[07/15] target-tricore: Add instructions of SRR opcode format - - - - --- 2014-07-07 Bastian Koppelmann New
[07/28] target/riscv: Convert RVXM insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[08/10] target-tricore: add FCALL instructions of the v1.6 ISA - - - - --- 2015-05-13 Bastian Koppelmann New
[08/10] target/tricore: Swap src and dst reg for RCRR_INSERT TriCore 1.6.2 insn and bugfixes - - - - --- 2023-08-26 Bastian Koppelmann New
[08/10] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' TriCore tests and cleanups - - - - --- 2023-09-13 Bastian Koppelmann New
[08/15] target-tricore: Add instructions of SSR opcode format - - - - --- 2014-07-07 Bastian Koppelmann New
[08/28] target/riscv: Convert RV32A insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[09/10] target-tricore: add FRET instructions of the v1.6 ISA - - - - --- 2015-05-13 Bastian Koppelmann New
[09/10] target/tricore: Remove CSFRs from cpu.h TriCore tests and cleanups - - - - --- 2023-09-13 Bastian Koppelmann New
[09/10] target/tricore: Replace cpu_*_code with translator_* TriCore 1.6.2 insn and bugfixes - - 1 - --- 2023-08-26 Bastian Koppelmann New
[09/15] target-tricore: Add instructions of SRRS and SLRO opcode format. - - - - --- 2014-07-07 Bastian Koppelmann New
[09/28] target/riscv: Convert RV64A insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[1/2] target/riscv: Fix FCLASS_D being treated as RV64 only target/riscv: Bugfixes found in decodetree conversion - - 2 - --- 2018-11-08 Bastian Koppelmann New
[1/2] target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2 tricore: IMASK/EXTR corner case fixes - - 1 - --- 2021-03-05 Bastian Koppelmann New
[1/3] target-tricore: add missing break in insn decode switch stmt - - - - --- 2016-03-01 Bastian Koppelmann New
[1/3] target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result - - - - --- 2015-05-22 Bastian Koppelmann New
[1/3] target/tricore: Use DisasContextBase API tricore: Convert to translate_loop - - 1 - --- 2019-06-17 Bastian Koppelmann New
[1/4] target-tricore: Make TRICORE_FEATURES implying others. - - - - --- 2014-11-13 Bastian Koppelmann New
[1/4] target-tricore: Several translator and cpu model fixes - - - - --- 2015-01-21 Bastian Koppelmann New
[1/4] target-tricore: target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs… - - - - --- 2015-01-21 Bastian Koppelmann New
[1/4] target/tricore: Fix out-of-bounds index in imask instruction TriCore bugfixes - - 1 - --- 2023-06-12 Bastian Koppelmann New
[1/4] target/tricore: Introduce priv tb flag TriCore Privilege Levels - - 1 - --- 2023-06-14 Bastian Koppelmann New
[1/5] target-tricore: Add instructions of BOL opcode format - - 1 - --- 2014-10-29 Bastian Koppelmann New
[1/5] target-tricore: Add trap handling - - - - --- 2016-02-11 Bastian Koppelmann New
[1/5] target-tricore: Added FTOUZ instruction - - - - --- 2016-10-06 Bastian Koppelmann New
[1/5] target-tricore: Cleanup and Bugfixes - - 1 - --- 2014-09-27 Bastian Koppelmann New
[1/5] target-tricore: Fix LOOP using wrong register for compare - - - - --- 2015-05-05 Bastian Koppelmann New
[1/5] target/tricore: Don't save pc in generate_qemu_excp TriCore fixes and gdbstub - - - - --- 2019-09-30 Bastian Koppelmann New
[1/5] target/tricore: Fix OPC2_32_RCRW_IMASK translation TriCore instruction bugfixes - - 1 - --- 2023-01-27 Bastian Koppelmann New
[1/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as first opcode - - - - --- 2015-02-25 Bastian Koppelmann New
[1/6] target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper - - - - --- 2015-02-10 Bastian Koppelmann New
[1/6] target/tricore: Add semihosting stub TriCore Semihosting - - - - --- 2023-10-15 Bastian Koppelmann New
[1/6] target/tricore: Introduce ISA 1.6.2 feature TriCore 1.6.2 Instructions 1 - - - --- 2023-06-10 Bastian Koppelmann New
[1/6] tests/tcg/tricore: Move asm tests into 'asm' directory TriCore PCXI/ICR register fixes - - - - --- 2023-05-19 Bastian Koppelmann New
[1/7] target-tricore: Add FPU infrastructure - - - - --- 2016-03-01 Bastian Koppelmann New
[1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 - - - - --- 2014-12-12 Bastian Koppelmann New
[10/10] target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA - - 1 - --- 2015-05-13 Bastian Koppelmann New
[10/10] target/tricore: Change effective address (ea) to target_ulong TriCore tests and cleanups - - - - --- 2023-09-13 Bastian Koppelmann New
[10/10] target/tricore: Fix FTOUZ being ISA v1.3.1 up TriCore 1.6.2 insn and bugfixes - - 1 - --- 2023-08-26 Bastian Koppelmann New
[10/15] target-tricore: Add instructions of SB opcode format - - - - --- 2014-07-07 Bastian Koppelmann New
[10/28] target/riscv: Convert RV32F insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[11/15] target-tricore: Add instructions of SBC and SBRN opcode format - - - - --- 2014-07-07 Bastian Koppelmann New
[11/28] target/riscv: Convert RV64F insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[12/15] target-tricore: Add instructions of SBR opcode format - - - - --- 2014-07-07 Bastian Koppelmann New
[12/28] target/riscv: Convert RV32D insns to decodetree target/riscv: Convert to decodetree - - - - --- 2018-10-12 Bastian Koppelmann New
[13/28] target/riscv: Convert RV64D insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[14/15] target-tricore: Add instructions of SLR, SSRO and SRO opcode format - - - - --- 2014-07-07 Bastian Koppelmann New
[14/28] target/riscv: Convert RV priv insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[15/15] target-tricore: Add instructions of SR opcode format - - - - --- 2014-07-07 Bastian Koppelmann New
[15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert to decodetree - - - - --- 2018-10-12 Bastian Koppelmann New
[16/28] target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert to decodetree - - - - --- 2018-10-12 Bastian Koppelmann New
[17/28] target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Convert to decodetree - - - - --- 2018-10-12 Bastian Koppelmann New
[18/28] target/riscv: Remove gen_jalr() target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[19/28] target/riscv: Replace gen_branch() with trans_branch() target/riscv: Convert to decodetree - - 1 - --- 2018-10-12 Bastian Koppelmann New
[2/2] target/riscv: Fix sfence.vm/a both available in any priv version target/riscv: Bugfixes found in decodetree conversion - - 2 - --- 2018-11-08 Bastian Koppelmann New
[2/2] target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 tricore: IMASK/EXTR corner case fixes - - 2 - --- 2021-03-05 Bastian Koppelmann New
[2/3] target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit - - - - --- 2016-03-01 Bastian Koppelmann New
[2/3] target-tricore: Make env a member of DisasContext tricore: Convert to translate_loop - - 1 - --- 2019-06-17 Bastian Koppelmann New
[2/3] target-tricore: fix msub32_q producing the wrong overflow bit - - - - --- 2015-05-22 Bastian Koppelmann New
[2/4] target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format - - - - --- 2014-11-13 Bastian Koppelmann New
[2/4] target-tricore: Add instructions of RR2 opcode format - - - - --- 2015-01-21 Bastian Koppelmann New
[2/4] target-tricore: calculate av bits before saturation - - - - --- 2015-01-21 Bastian Koppelmann New
[2/4] target/tricore: Correctly fix saving PSW.CDE to CSA on call TriCore bugfixes - - - - --- 2023-06-12 Bastian Koppelmann New
[2/4] target/tricore: Implement privilege level for all insns TriCore Privilege Levels - - 1 - --- 2023-06-14 Bastian Koppelmann New
[2/5] target-tricore: Add instructions of ABS, ABSB opcode format - - - - --- 2014-09-27 Bastian Koppelmann New
[2/5] target-tricore: Add instructions of BRC opcode format - - 1 - --- 2014-10-29 Bastian Koppelmann New
[2/5] target-tricore: Added MADD.F and MSUB.F instructions - - - - --- 2016-10-06 Bastian Koppelmann New
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