Show patches with: Archived = No       |   430333 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v2,8/8] iotests: remove the check-block.sh script iotests: make meson aware of individual I/O tests - - 1 - --- 2023-03-03 Daniel P. Berrangé New
[v2,7/8] iotests: register each I/O test separately with meson iotests: make meson aware of individual I/O tests - - 1 - --- 2023-03-03 Daniel P. Berrangé New
[v2,6/8] iotests: always use a unique sub-directory per test iotests: make meson aware of individual I/O tests - - 1 - --- 2023-03-03 Daniel P. Berrangé New
[v2,5/8] iotests: connect stdin to /dev/null when running tests iotests: make meson aware of individual I/O tests - - 1 - --- 2023-03-03 Daniel P. Berrangé New
[v2,4/8] iotests: print TAP protocol version when reporting tests iotests: make meson aware of individual I/O tests - - 2 - --- 2023-03-03 Daniel P. Berrangé New
[v2,3/8] iotests: strip subdir path when listing tests iotests: make meson aware of individual I/O tests - - 1 - --- 2023-03-03 Daniel P. Berrangé New
[v2,2/8] iotests: allow test discovery before building iotests: make meson aware of individual I/O tests - - 2 - --- 2023-03-03 Daniel P. Berrangé New
[v2,1/8] iotests: explicitly pass source/build dir to 'check' command iotests: make meson aware of individual I/O tests - - 1 - --- 2023-03-03 Daniel P. Berrangé New
[v2] hw: arm: Support direct boot for Linux/arm64 EFI zboot images [v2] hw: arm: Support direct boot for Linux/arm64 EFI zboot images - - - - --- 2023-03-03 Ard Biesheuvel New
[v6] audio/pwaudio.c: Add Pipewire audio backend for QEMU [v6] audio/pwaudio.c: Add Pipewire audio backend for QEMU - - - - --- 2023-03-03 Dorinda Bassey New
[v11,5/5] riscv: Correctly set the device-tree entry 'mmu-type' riscv: Allow user to set the satp mode - - 4 - --- 2023-03-03 Alexandre Ghiti New
[v11,4/5] riscv: Introduce satp mode hw capabilities riscv: Allow user to set the satp mode - - 4 - --- 2023-03-03 Alexandre Ghiti New
[v11,3/5] riscv: Allow user to set the satp mode riscv: Allow user to set the satp mode 1 - 3 - --- 2023-03-03 Alexandre Ghiti New
[v11,2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Allow user to set the satp mode - - 4 - --- 2023-03-03 Alexandre Ghiti New
[v11,1/5] riscv: Pass Object to register_cpu_props instead of DeviceState riscv: Allow user to set the satp mode - - 4 - --- 2023-03-03 Alexandre Ghiti New
[2/2] tests/avocado: Test Xen guest support under KVM tests/avocado: Test Xen guest support under KVM - - - - --- 2023-03-03 David Woodhouse New
[1/2] tests/avocado: Add Fedora 34 distro, including kernel/initrd checksums tests/avocado: Test Xen guest support under KVM - - - - --- 2023-03-03 David Woodhouse New
vdpa: fix emulated guest announce feature status handling vdpa: fix emulated guest announce feature status handling - - - - --- 2023-03-03 Gautam Dawar New
[RESEND,v6,5/5] migration: Reduce time of loading non-iterable vmstate migration: reduce time of loading non-iterable vmstate - - - - --- 2023-03-03 Chuang Xu New
[RESEND,v6,4/5] memory: Add sanity check in address_space_to_flatview migration: reduce time of loading non-iterable vmstate - - - - --- 2023-03-03 Chuang Xu New
[RESEND,v6,3/5] memory: Introduce memory_region_transaction_do_commit() migration: reduce time of loading non-iterable vmstate - - - - --- 2023-03-03 Chuang Xu New
[RESEND,v6,2/5] rcu: Introduce rcu_read_is_locked() migration: reduce time of loading non-iterable vmstate - - - - --- 2023-03-03 Chuang Xu New
[RESEND,v6,1/5] memory: Reference as->current_map directly in memory commit migration: reduce time of loading non-iterable vmstate - - - - --- 2023-03-03 Chuang Xu New
[v6,5/5] migration: Reduce time of loading non-iterable vmstate migration: reduce time of loading non-iterable vmstate - - - - --- 2023-03-03 Chuang Xu New
[v6,4/5] memory: Add sanity check in address_space_to_flatview migration: reduce time of loading non-iterable vmstate - - - - --- 2023-03-03 Chuang Xu New
[v6,3/5] memory: Introduce memory_region_transaction_do_commit() migration: reduce time of loading non-iterable vmstate - - - - --- 2023-03-03 Chuang Xu New
[v6,2/5] rcu: Introduce rcu_read_is_locked() migration: reduce time of loading non-iterable vmstate - - - - --- 2023-03-03 Chuang Xu New
[v6,1/5] memory: Reference as->current_map directly in memory commit migration: reduce time of loading non-iterable vmstate - - - - --- 2023-03-03 Chuang Xu New
[v3,6/6] gitlab-ci.d/crossbuilds: Drop the 32-bit arm system emulation jobs Deprecate support for 32-bit x86 and arm hosts - - 3 - --- 2023-03-03 Thomas Huth New
[v3,5/6] docs/about/deprecated: Deprecate the qemu-system-arm binary Deprecate support for 32-bit x86 and arm hosts - - 2 - --- 2023-03-03 Thomas Huth New
[v3,4/6] docs/about/deprecated: Deprecate 32-bit arm hosts for system emulation Deprecate support for 32-bit x86 and arm hosts - - 2 - --- 2023-03-03 Thomas Huth New
[v3,3/6] gitlab-ci.d/crossbuilds: Drop the i386 jobs Deprecate support for 32-bit x86 and arm hosts - - 2 - --- 2023-03-03 Thomas Huth New
[v3,2/6] docs/about/deprecated: Deprecate the qemu-system-i386 binary Deprecate support for 32-bit x86 and arm hosts - - 2 - --- 2023-03-03 Thomas Huth New
[v3,1/6] docs/about/deprecated: Deprecate 32-bit x86 hosts Deprecate support for 32-bit x86 and arm hosts - - 2 - --- 2023-03-03 Thomas Huth New
[v2] tcg: Include "qemu/timer.h" for profile_getclock [v2] tcg: Include "qemu/timer.h" for profile_getclock - - 2 - --- 2023-03-03 Richard W.M. Jones New
[PULL,59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,55/59] target/riscv/csr.c: simplify mctr() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,54/59] target/riscv/csr.c: use env_archcpu() in ctr() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,53/59] target/riscv: Export Svadu property [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,52/59] target/riscv: Add *envcfg.HADE related check in address translation [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,51/59] target/riscv: Add *envcfg.PBMTE related check in address translation [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,50/59] target/riscv: Add csr support for svadu [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensio… [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,47/59] hw/riscv: Move the dtb load bits outside of create_fdt() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,46/59] hw/riscv: Skip re-generating DT nodes for a given DTB [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,45/59] target/riscv: Add support for Zicond extension [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,42/59] target/riscv: Group all predicate() routines together [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,41/59] target/riscv: Drop priv level check in mseccfg predicate() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,40/59] target/riscv: Allow debugger to access sstc CSRs [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,38/59] target/riscv: Allow debugger to access seed CSR [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,37/59] target/riscv: Allow debugger to access user timer and counter CSRs [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,33/59] target/riscv: Simplify getting RISCVCPU pointer from env [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,31/59] target/riscv: Use 'bool' type for read_only [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,30/59] target/riscv: Coding style fixes in csr.c [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,28/59] target/riscv: gdbstub: Minor change for better readability [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,27/59] target/riscv: Use g_assert() for the predicate() NULL check [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,24/59] target/riscv: Expose properties for Zv* extensions [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,22/59] target/riscv: Fix check for vector load/store instructions when EEW=64 [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,21/59] target/riscv: Add support for Zvfh/zvfhmin extensions [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,20/59] target/riscv: Remove redundunt check for zve32f and zve64f [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,18/59] target/riscv: Simplify check for Zve32f and Zve64f [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,17/59] target/riscv: Indent fixes in cpu.c [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,16/59] target/riscv: Add property check for Zvfh{min} extensions [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,15/59] target/riscv: Fix relationship between V, Zve*, F and D [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,14/59] target/riscv: Add cfg properties for Zv* extensions [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,11/59] target/riscv: Fix the relationship between Zfhmin and Zfh [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,10/59] target/riscv/cpu: remove CPUArchState::features and friends [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,09/59] target/riscv: remove RISCV_FEATURE_MMU [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,07/59] target/riscv: remove RISCV_FEATURE_PMP [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,06/59] target/riscv: remove RISCV_FEATURE_EPMP [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,04/59] target/riscv: remove RISCV_FEATURE_DEBUG [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,03/59] target/riscv: allow MISA writes as experimental [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 5 - --- 2023-03-03 Palmer Dabbelt New
[PULL,02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 3 - --- 2023-03-03 Palmer Dabbelt New
[PULL,01/59] target/riscv: introduce riscv_cpu_cfg() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,00/59] Fifth RISC-V PR for QEMU 8.0 - - - - --- 2023-03-03 Palmer Dabbelt New
[v2] vfio: Fix vfio_get_dev_region() trace event [v2] vfio: Fix vfio_get_dev_region() trace event - 1 1 - --- 2023-03-03 Cédric Le Goater New
[v2,6/6] target/i386: Add support for PREFETCHIT0/1 in CPUID enumeration target/i386: Support new Intel platform Instructions in CPUID enumeration - - - - --- 2023-03-03 Tao Su New
[v2,5/6] target/i386: Add support for AVX-NE-CONVERT in CPUID enumeration target/i386: Support new Intel platform Instructions in CPUID enumeration - - - - --- 2023-03-03 Tao Su New
[v2,4/6] target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration target/i386: Support new Intel platform Instructions in CPUID enumeration - - - - --- 2023-03-03 Tao Su New
[v2,3/6] target/i386: Add support for AVX-IFMA in CPUID enumeration target/i386: Support new Intel platform Instructions in CPUID enumeration - - - - --- 2023-03-03 Tao Su New
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