Show patches with: Archived = No       |   430675 patches
« 1 2 ... 551 552 553 … 4306 4307 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v6,27/30] riscv: sifive_u: Instantiate OTP memory with a serial number [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,26/30] riscv: sifive: Implement a model for SiFive FU540 OTP [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-27 Bin Meng Superseded
[v6,25/30] riscv: roms: Update default bios for sifive_u machine [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,24/30] riscv: sifive_u: Change UART node name in device tree [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,23/30] riscv: sifive_u: Update UART base addresses and IRQs [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property 1 - 2 - --- 2019-08-27 Bin Meng Superseded
[v6,22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,21/30] riscv: sifive_u: Add PRCI block to the SoC [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,19/30] riscv: sifive: Implement PRCI model for FU540 [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,18/30] riscv: sifive_u: Update PLIC hart topology configuration string [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,16/30] riscv: sifive_u: Set the minimum number of cpus to 2 [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-27 Bin Meng Superseded
[v6,14/30] riscv: hart: Extract hart realize to a separate routine [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 2 - --- 2019-08-27 Bin Meng Superseded
[v6,12/30] riscv: sifive_e: Drop sifive_mmio_emulate() [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,11/30] riscv: sifive_e: prci: Update the PRCI register block size [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 2 - --- 2019-08-27 Bin Meng Superseded
[v6,10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property 1 - 2 - --- 2019-08-27 Bin Meng Superseded
[v6,09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 2 - --- 2019-08-27 Bin Meng Superseded
[v6,08/30] riscv: sifive_u: Remove the unnecessary include of prci header [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,04/30] riscv: hw: Change create_fdt() to return void [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 3 - --- 2019-08-27 Bin Meng Superseded
[v6,03/30] riscv: hw: Remove not needed PLIC properties in device tree [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 2 - --- 2019-08-27 Bin Meng Superseded
[v6,02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-27 Bin Meng Superseded
[v5,30/30] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,28/30] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,26/30] riscv: sifive: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-23 Bin Meng Superseded
[v5,25/30] riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,24/30] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,23/30] riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-08-23 Bin Meng Superseded
[v5,22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,21/30] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,19/30] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,18/30] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,17/30] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-23 Bin Meng Superseded
[v5,14/30] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-23 Bin Meng Superseded
[v5,11/30] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-23 Bin Meng Superseded
[v5,10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-08-23 Bin Meng Superseded
[v5,09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-23 Bin Meng Superseded
[v5,08/30] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,04/30] riscv: hw: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 3 - --- 2019-08-23 Bin Meng Superseded
[v5,03/30] riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-23 Bin Meng Superseded
[v5,02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v5,01/30] riscv: hw: Remove superfluous "linux, phandle" property riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-23 Bin Meng Superseded
[v4,28/28] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,26/28] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,25/28] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,24/28] riscv: sifive: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-19 Bin Meng Superseded
[v4,23/28] riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-19 Bin Meng Superseded
[v4,22/28] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,21/28] riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-08-19 Bin Meng Superseded
[v4,20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,19/28] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-19 Bin Meng Superseded
[v4,18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,17/28] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-19 Bin Meng Superseded
[v4,16/28] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,15/28] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-19 Bin Meng Superseded
[v4,12/28] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-19 Bin Meng Superseded
[v4,09/28] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-19 Bin Meng Superseded
[v4,08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-08-19 Bin Meng Superseded
[v4,07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,06/28] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,04/28] riscv: hw: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 3 - --- 2019-08-19 Bin Meng Superseded
[v4,03/28] riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-19 Bin Meng Superseded
[v4,02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,01/28] riscv: hw: Remove superfluous "linux, phandle" property [v4,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-19 Bin Meng Superseded
[2/2] riscv: Resolve full path of the given bios image riscv: Fix "-L" not working for bios image search path - - 1 - --- 2019-08-16 Bin Meng New
[1/2] riscv: Add a helper routine for finding firmware riscv: Fix "-L" not working for bios image search path - - - - --- 2019-08-16 Bin Meng New
[v4] riscv: hmp: Add a command to show virtual memory mappings [v4] riscv: hmp: Add a command to show virtual memory mappings 1 - 1 - --- 2019-08-14 Bin Meng New
[v3] riscv: hmp: Add a command to show virtual memory mappings [v3] riscv: hmp: Add a command to show virtual memory mappings 1 - - - --- 2019-08-12 Bin Meng Superseded
[v3,28/28] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,27/28] riscv: virt: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 3 - --- 2019-08-11 Bin Meng Superseded
[v3,25/28] riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-11 Bin Meng Superseded
[v3,24/28] riscv: sifive_u: Support loading initramfs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-11 Bin Meng Superseded
[v3,23/28] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,22/28] riscv: sifive_u: Generate an aliases node in the device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,21/28] riscv: sifive_u: Update UART and ethernet node clock properties riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,19/28] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,18/28] riscv: hw: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,17/28] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,16/28] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,14/28] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,13/28] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-11 Bin Meng Superseded
[v3,12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-08-11 Bin Meng Superseded
[v3,11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,10/28] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
« 1 2 ... 551 552 553 … 4306 4307 »