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Delegate
------
Nobody
jgarzik
arnd
ymano
smfrench
jlayton
tseliot
ogasawara
amitk
awhitcroft
mst
dayangkun
jwboyer
jwboyer
colinking
colinking
azummo
dwmw2
rtg
sconklin
smb
aliguori
bradf
galak
galak
demarchi
ms
bhundven
chbs
kengyu
kadlec
pdp
regit
jabk
laforge
laforge
tonyb
sfr
alai
zecke
zecke
__damien__
luka
luka
prafulla@marvell.com
cyrus
PeterHuewe
kiho
jow
jow
ypwong
nico
dedeckeh
dedeckeh
yousong
yousong
tomcwarren
mb
mrchuck
vineetg76
computersforpeace
Noltari
Noltari
patrick_delaunay
ee07b291
ldir
ldir
stefanct
zhouhan
carldani
blp
ffainelli
ffainelli
regXboi
bbrezillon
pravin
mkp
jpettit
phil
mkresin
mkresin
thess
thess
fbarrat
fbarrat
linville
jesse
tjaalton
esben
abrodkin
abrodkin
diproiettod
tbot
stephenfin
vriera
darball1
sammj
ajd
jogo
jogo
bhelgaas
blogic
blogic
oohal
russellb
ptomsich
agraf
joestringer
davem
davem
davem
mwalle
naveen
pchotard
tagr
tagr
tagr
pepe2k
pepe2k
arj
arj
andmur01
amitay
matttbe
pabeni
istokes
aparcar
Ansuel
goliath
martineau
tytso
danielschwierzeck
mariosix
dcaratti
ovsrobot
ovsrobot
aserdean
XiaoYang
khem
hs
mkorpershoek
tpetazzoni
marex
liwang
robimarko
danielhb
groug
apritzel
mmichelson
npiggin
pareddja
atishp
netdrv
mkubecek
stintel
stintel
jkicinski
cpitchen
maximeh
dsa
jstancek
pm215
bpf
jonhunter
shettyg
lorpie01
acelan
wigyori
wigyori
apopple
dja
alexhung
lynxis
lynxis
brgl
brgl
peda
akodanev
narmstrong
981213
0andriy
chunkeey
snowpatch_ozlabs
snowpatch_ozlabs
snowpatch_ozlabs
aivanov
atishp04
shemminger
horms
monstr
vigneshr
mraynal
blocktrron
stewart
stewart
wsa
sjg
rfried
ehristev
akumar
freenix
Jaehoon
jacmet
ivanhu
kevery
rsalvaterra
adrianschmutzler
xypron
hegdevasant
hegdevasant
metan
bmeng
jagan
ukleinek
ukleinek
ag
rmilecki
rmilecki
prom
kabel
arbab
pablo
pablo
trini
apconole
rw
rw
abelloni
wbx
Hauke
Hauke
legoater
legoater
legoater
chleroy
svanheule
bjonglez
ynezz
aik
pevik
sbabic
sbabic
xback
xback
richiejp
dangole
dangole
forty
anuppatel
anuppatel
acer
echaudron
benh
rgrimm
next_ghost
segher
passgat
pratyush
jms
jms
jms
ymorin
ymorin
mans0n
ruscur
Andes
jmberg
festevam
jk
jk
jk
jk
linusw
linusw
numans
xuyang
matthias_bgg
tambarus
stroese
kubu
strlen
strlen
imaximets
apalos
dceara
pbrobinson
spectrum
cazzacarna
neocturne
aldot
TIENFONG
mpe
arnout
ktraynor
robh
nbd
nbd
calebccff
anguy11
paulus
jm
Apply
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[5/5] target-tricore: add opd trap generation
- - - -
-
-
-
2016-02-11
Bastian Koppelmann
New
[4/5] target-tricore: add illegal opcode trap generation
- - - -
-
-
-
2016-02-11
Bastian Koppelmann
New
[3/5] target-tricore: add context managment trap generation
- - - -
-
-
-
2016-02-11
Bastian Koppelmann
New
[2/5] target-tricore: Save the pc before CSA operations for exceptions
- - - -
-
-
-
2016-02-11
Bastian Koppelmann
New
[1/5] target-tricore: Add trap handling
- - - -
-
-
-
2016-02-11
Bastian Koppelmann
New
checkpatch: Perl 5.22 deprecation fixes
- - - -
-
-
-
2015-09-04
Bastian Koppelmann
New
[PULL,1/1] target-tricore: fix depositing bits from PCXI into ICR
- - - -
-
-
-
2015-06-29
Bastian Koppelmann
New
[PULL,0/1] tricore-patches
- - - -
-
-
-
2015-06-29
Bastian Koppelmann
New
[PULL,3/3] target-tricore: fix BOL_ST_H_LONGOFF using ld
- - - -
-
-
-
2015-05-30
Bastian Koppelmann
New
[PULL,2/3] target-tricore: fix msub32_q producing the wrong overflow bit
- - - -
-
-
-
2015-05-30
Bastian Koppelmann
New
[PULL,1/3] target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result
- - - -
-
-
-
2015-05-30
Bastian Koppelmann
New
[PULL,0/3] tricore-patches
- - - -
-
-
-
2015-05-30
Bastian Koppelmann
New
[PULL,10/10] target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[PULL,09/10] target-tricore: add FRET instructions of the v1.6 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[PULL,08/10] target-tricore: add FCALL instructions of the v1.6 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[PULL,07/10] target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[PULL,06/10] target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[PULL,05/10] target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[PULL,04/10] target-tricore: add CMPSWP instructions of the v1.6.1 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[PULL,03/10] target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[PULL,02/10] target-tricore: introduce ISA v1.6.1 feature
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[PULL,01/10] target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[PULL,00/10] tricore-patches
- - - -
-
-
-
2015-05-22
Bastian Koppelmann
New
[3/3] target-tricore: fix BOL_ST_H_LONGOFF using ld
- - - -
-
-
-
2015-05-22
Bastian Koppelmann
New
[2/3] target-tricore: fix msub32_q producing the wrong overflow bit
- - - -
-
-
-
2015-05-22
Bastian Koppelmann
New
[1/3] target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result
- - - -
-
-
-
2015-05-22
Bastian Koppelmann
New
[v2,10/10] target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[v2,09/10] target-tricore: add FRET instructions of the v1.6 ISA
- - - -
-
-
-
2015-05-22
Bastian Koppelmann
New
[v2,08/10] target-tricore: add FCALL instructions of the v1.6 ISA
- - - -
-
-
-
2015-05-22
Bastian Koppelmann
New
[v2,07/10] target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[v2,06/10] target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[v2,05/10] target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[v2,04/10] target-tricore: add CMPSWP instructions of the v1.6.1 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[v2,03/10] target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[v2,02/10] target-tricore: introduce ISA v1.6.1 feature
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[v2,01/10] target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3
- - 1 -
-
-
-
2015-05-22
Bastian Koppelmann
New
[10/10] target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
- - 1 -
-
-
-
2015-05-13
Bastian Koppelmann
New
[09/10] target-tricore: add FRET instructions of the v1.6 ISA
- - - -
-
-
-
2015-05-13
Bastian Koppelmann
New
[08/10] target-tricore: add FCALL instructions of the v1.6 ISA
- - - -
-
-
-
2015-05-13
Bastian Koppelmann
New
[07/10] target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
- - 1 -
-
-
-
2015-05-13
Bastian Koppelmann
New
[06/10] target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
- - 1 -
-
-
-
2015-05-13
Bastian Koppelmann
New
[05/10] target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
- - 1 -
-
-
-
2015-05-13
Bastian Koppelmann
New
[04/10] target-tricore: add CMPSWP instructions of the v1.6.1 ISA
- - 1 -
-
-
-
2015-05-13
Bastian Koppelmann
New
[03/10] target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
- - 1 -
-
-
-
2015-05-13
Bastian Koppelmann
New
[02/10] target-tricore: introduce ISA v1.6.1 feature
- - 1 -
-
-
-
2015-05-13
Bastian Koppelmann
New
[01/10] target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3
- - 1 -
-
-
-
2015-05-13
Bastian Koppelmann
New
[PULL,5/5] target-tricore: fix rfe not restoring the PC
- - - -
-
-
-
2015-05-11
Bastian Koppelmann
New
[PULL,4/5] target-tricore: fix rslcx restoring the upper context instead of the lower
- - - -
-
-
-
2015-05-11
Bastian Koppelmann
New
[PULL,3/5] target-tricore: fix BO_OFF10_SEXT calculating the wrong offset
- - - -
-
-
-
2015-05-11
Bastian Koppelmann
New
[PULL,2/5] target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access inst…
- - - -
-
-
-
2015-05-11
Bastian Koppelmann
New
[PULL,1/5] target-tricore: Fix LOOP using wrong register for compare
- - - -
-
-
-
2015-05-11
Bastian Koppelmann
New
[PULL,0/5] tricore-patches
- - - -
-
-
-
2015-05-11
Bastian Koppelmann
New
[5/5] target-tricore: fix rfe not restoring the PC
- - - -
-
-
-
2015-05-05
Bastian Koppelmann
New
[4/5] target-tricore: fix rslcx restoring the upper context instead of the lower
- - - -
-
-
-
2015-05-05
Bastian Koppelmann
New
[3/5] target-tricore: fix BO_OFF10_SEXT calculating the wrong offset
- - - -
-
-
-
2015-05-05
Bastian Koppelmann
New
[2/5] target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of…
- - - -
-
-
-
2015-05-05
Bastian Koppelmann
New
[1/5] target-tricore: Fix LOOP using wrong register for compare
- - - -
-
-
-
2015-05-05
Bastian Koppelmann
New
[PULL] target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..
- - - -
-
-
-
2015-03-30
Bastian Koppelmann
New
[PULL] tricore patches for 2.3-rc2
- - - -
-
-
-
2015-03-30
Bastian Koppelmann
New
target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..
- - - -
-
-
-
2015-03-27
Bastian Koppelmann
New
[PULL,4/4] target-tricore: properly fix dvinit_b/h_13
- - - -
-
-
-
2015-03-24
Bastian Koppelmann
New
[PULL,3/4] target-tricore: fix RRPW_DEXTR using wrong reg
- - - -
-
-
-
2015-03-24
Bastian Koppelmann
New
[PULL,2/4] target-tricore: fix DVINIT_HU/BU calculating overflow before result
- - - -
-
-
-
2015-03-24
Bastian Koppelmann
New
[PULL,1/4] target-tricore: Fix two helper functions (clang warnings)
- - - -
-
-
-
2015-03-24
Bastian Koppelmann
New
[PULL,0/4] tricore-patches for 2.3-rc1
- - - -
-
-
-
2015-03-24
Bastian Koppelmann
New
target-tricore: properly fix dvinit_b/h_13
- - - -
-
-
-
2015-03-23
Bastian Koppelmann
New
target-tricore: fix RRPW_DEXTR using wrong reg
- - - -
-
-
-
2015-03-23
Bastian Koppelmann
New
target-tricore: fix DVINIT_HU/BU calculating overflow before result
- - - -
-
-
-
2015-03-20
Bastian Koppelmann
New
[PULL,6/6] target-tricore: Add instructions of SYS opcode format
- - - -
-
-
-
2015-03-16
Bastian Koppelmann
New
[PULL,5/6] target-tricore: Add instructions of RRRW opcode format
- - 1 -
-
-
-
2015-03-16
Bastian Koppelmann
New
[PULL,4/6] target-tricore: Add instructions of RRRR opcode format
- - 1 -
-
-
-
2015-03-16
Bastian Koppelmann
New
[PULL,3/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode
- - 1 -
-
-
-
2015-03-16
Bastian Koppelmann
New
[PULL,2/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as first opcode
- - 1 -
-
-
-
2015-03-16
Bastian Koppelmann
New
[PULL,1/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as first opcode
- - 1 -
-
-
-
2015-03-16
Bastian Koppelmann
New
[PULL,0/6] tricore patches for 2.3
- - - -
-
-
-
2015-03-16
Bastian Koppelmann
New
qemu-system-ppc TCG assert with git master
- - - -
-
-
-
2015-03-12
Bastian Koppelmann
New
[PULL,6/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode
- - 1 -
-
-
-
2015-03-03
Bastian Koppelmann
New
[PULL,5/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode
- - 1 -
-
-
-
2015-03-03
Bastian Koppelmann
New
[PULL,4/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode
- - 1 -
-
-
-
2015-03-03
Bastian Koppelmann
New
[PULL,3/6] target-tricore: Add instructions of RRR2 opcode format
- - 1 -
-
-
-
2015-03-03
Bastian Koppelmann
New
[PULL,2/6] target-tricore: fix msub32_suov return wrong results
- - 1 -
-
-
-
2015-03-03
Bastian Koppelmann
New
[PULL,1/6] target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper
- - 1 -
-
-
-
2015-03-03
Bastian Koppelmann
New
[PULL,0/6] tricore patches for 2.3
- - - -
-
-
-
2015-03-03
Bastian Koppelmann
New
[6/6] target-tricore: Add instructions of SYS opcode format
- - - -
-
-
-
2015-02-25
Bastian Koppelmann
New
[5/6] target-tricore: Add instructions of RRRW opcode format
- - - -
-
-
-
2015-02-25
Bastian Koppelmann
New
[4/6] target-tricore: Add instructions of RRRR opcode format
- - - -
-
-
-
2015-02-25
Bastian Koppelmann
New
[3/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode
- - - -
-
-
-
2015-02-25
Bastian Koppelmann
New
[2/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as first opcode
- - - -
-
-
-
2015-02-25
Bastian Koppelmann
New
[1/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as first opcode
- - - -
-
-
-
2015-02-25
Bastian Koppelmann
New
[v2,6/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode
- - - -
-
-
-
2015-02-11
Bastian Koppelmann
New
[v2,5/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode
- - - -
-
-
-
2015-02-11
Bastian Koppelmann
New
[v2,4/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode
- - - -
-
-
-
2015-02-11
Bastian Koppelmann
New
[v2,3/6] target-tricore: Add instructions of RRR2 opcode format
- - - -
-
-
-
2015-02-11
Bastian Koppelmann
New
[v2,2/6] target-tricore: fix msub32_suov return wrong results
- - - -
-
-
-
2015-02-11
Bastian Koppelmann
New
[v2,1/6] target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper
- - - -
-
-
-
2015-02-11
Bastian Koppelmann
New
[6/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode
- - - -
-
-
-
2015-02-10
Bastian Koppelmann
New
[5/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode
- - - -
-
-
-
2015-02-10
Bastian Koppelmann
New
[4/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode
- - - -
-
-
-
2015-02-10
Bastian Koppelmann
New
[3/6] target-tricore: Add instructions of RRR2 opcode format
- - - -
-
-
-
2015-02-10
Bastian Koppelmann
New
[2/6] target-tricore: fix msub32_suov return wrong results
- - - -
-
-
-
2015-02-10
Bastian Koppelmann
New
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