Show patches with: Archived = No       |   430128 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,06/10] RISC-V: Add misa to DisasContext [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,07/10] RISC-V: Add misa.MAFD checks to translate [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,08/10] RISC-V: Add misa runtime write support [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,09/10] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer [PR,RFC] RISC-V Patches for 3.2, Part 3 - - - - --- 2019-01-30 Palmer Dabbelt New
[PULL,10/10] target/riscv: fix counter-enable checks in ctr() [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL] RISC-V Patches for 3.2, Part 3 [PULL] RISC-V Patches for 3.2, Part 3 - - - - --- 2019-02-02 Palmer Dabbelt New
[PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,02/10] RISC-V: Mark mstatus.fs dirty [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,03/10] RISC-V: Implement mstatus.TSR/TW/TVM [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - - - --- 2019-02-02 Palmer Dabbelt New
[PULL,04/10] RISC-V: Use riscv prefix consistently on cpu helpers [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,05/10] RISC-V: Add priv_ver to DisasContext [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,06/10] RISC-V: Add misa to DisasContext [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,07/10] RISC-V: Add misa.MAFD checks to translate [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,08/10] RISC-V: Add misa runtime write support [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,09/10] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - - - --- 2019-02-02 Palmer Dabbelt New
[PULL,10/10] target/riscv: fix counter-enable checks in ctr() [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1 [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1 - - - - --- 2019-02-13 Palmer Dabbelt New
[PULL,01/11] RISC-V: Split out mstatus_fs from tb_flags [PULL,01/11] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,02/11] RISC-V: Mark mstatus.fs dirty Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,03/11] RISC-V: Implement mstatus.TSR/TW/TVM Untitled series #91747 - - - - --- 2019-02-13 Palmer Dabbelt New
[PULL,04/11] RISC-V: Use riscv prefix consistently on cpu helpers Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,05/11] RISC-V: Add priv_ver to DisasContext Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,06/11] RISC-V: Add misa to DisasContext Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,07/11] RISC-V: Add misa.MAFD checks to translate Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,08/11] RISC-V: Add misa runtime write support Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,09/11] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer Untitled series #91747 - - - - --- 2019-02-13 Palmer Dabbelt New
[PULL,10/11] target/riscv: fix counter-enable checks in ctr() Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,11/11] riscv: Ensure the kernel start address is correctly cast Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,01/35] target/riscv: Move CPURISCVState pointer to DisasContext target/riscv: Convert to decodetree - - 3 - --- 2019-02-13 Palmer Dabbelt New
[v7,02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,03/35] target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert to decodetree 1 - 2 - --- 2019-02-13 Palmer Dabbelt New
[v7,04/35] target/riscv: Convert RV32I load/store insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,05/35] target/riscv: Convert RV64I load/store insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,06/35] target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,07/35] target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,08/35] target/riscv: Convert RVXI csr insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,09/35] target/riscv: Convert RVXM insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,10/35] target/riscv: Convert RV32A insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,11/35] target/riscv: Convert RV64A insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,12/35] target/riscv: Convert RV32F insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,13/35] target/riscv: Convert RV64F insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,14/35] target/riscv: Convert RV32D insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,15/35] target/riscv: Convert RV64D insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,16/35] target/riscv: Convert RV priv insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,20/35] target/riscv: Remove gen_jalr() target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,21/35] target/riscv: Remove manual decoding from gen_branch() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,22/35] target/riscv: Remove manual decoding from gen_load() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,23/35] target/riscv: Remove manual decoding from gen_store() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,26/35] target/riscv: Remove shift and slt insn manual decoding target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,27/35] target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,28/35] target/riscv: Rename trans_arith to gen_arith target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,29/35] target/riscv: Remove gen_system() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,30/35] target/riscv: Remove decode_RV32_64G() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,31/35] target/riscv: Convert @cs_2 insns to share translation functions target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,35/35] target/riscv: Remaining rvc insn reuse 32 bit translators target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL] target/riscv: Convert to decodetree [PULL] target/riscv: Convert to decodetree - - - - --- 2019-03-01 Palmer Dabbelt New
[PULL,01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC [PULL,01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,02/34] target/riscv: Convert RVXI branch insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 2 - --- 2019-03-01 Palmer Dabbelt New
[PULL,03/34] target/riscv: Convert RV32I load/store insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,04/34] target/riscv: Convert RV64I load/store insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,05/34] target/riscv: Convert RVXI arithmetic insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,06/34] target/riscv: Convert RVXI fence insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,07/34] target/riscv: Convert RVXI csr insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,08/34] target/riscv: Convert RVXM insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,09/34] target/riscv: Convert RV32A insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,10/34] target/riscv: Convert RV64A insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,11/34] target/riscv: Convert RV32F insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,12/34] target/riscv: Convert RV64F insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,13/34] target/riscv: Convert RV32D insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,14/34] target/riscv: Convert RV64D insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,15/34] target/riscv: Convert RV priv insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,19/34] target/riscv: Remove gen_jalr() [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,20/34] target/riscv: Remove manual decoding from gen_branch() [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,21/34] target/riscv: Remove manual decoding from gen_load() [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,22/34] target/riscv: Remove manual decoding from gen_store() [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,25/34] target/riscv: Remove shift and slt insn manual decoding [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,26/34] target/riscv: Remove manual decoding of RV32/64M insn [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,27/34] target/riscv: Rename trans_arith to gen_arith [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,28/34] target/riscv: Remove gen_system() [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,29/34] target/riscv: Remove decode_RV32_64G() [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,30/34] target/riscv: Convert @cs_2 insns to share translation functions [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,34/34] target/riscv: Remaining rvc insn reuse 32 bit translators [PULL] target/riscv: Convert to decodetree - - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL] target/riscv: Convert to decodetree [PULL] target/riscv: Convert to decodetree - - - - --- 2019-03-12 Palmer Dabbelt New
[PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-12 Palmer Dabbelt New
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