Show patches with: Series = Add RISC-V vector cryptographic instruction set support       |    State = Action Required       |    Archived = No       |   16 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v4,16/17] target/riscv: Add Zvksed ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New
[v4,15/17] crypto: Add SM4 constant parameter CK Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New
[v4,14/17] crypto: Create sm4_subword Add RISC-V vector cryptographic instruction set support - - 2 - --- 2023-06-22 Max Chou New
[v4,13/17] target/riscv: Add Zvkg ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New
[v4,12/17] target/riscv: Add Zvksh ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New
[v4,11/17] target/riscv: Add Zvknh ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New
[v4,10/17] target/riscv: Add Zvkned ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New
[v4,09/17] target/riscv: Add Zvbb ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New
[v4,08/17] tcg: Fix temporary variable in tcg_gen_gvec_andcs Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New
[v4,07/17] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New
[v4,06/17] target/riscv: Refactor translation of vector-widening instruction Add RISC-V vector cryptographic instruction set support - - 2 - --- 2023-06-22 Max Chou New
[v4,05/17] target/riscv: Move vector translation checks Add RISC-V vector cryptographic instruction set support - - 2 - --- 2023-06-22 Max Chou New
[v4,04/17] target/riscv: Add Zvbc ISA extension support Add RISC-V vector cryptographic instruction set support - - - - --- 2023-06-22 Max Chou New
[v4,03/17] target/riscv: Remove redundant "cpu_vl == 0" checks Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New
[v4,02/17] target/riscv: Refactor vector-vector translation macro Add RISC-V vector cryptographic instruction set support - - 3 - --- 2023-06-22 Max Chou New
[v4,01/17] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-22 Max Chou New