Show patches with: Series = [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw       |    State = Action Required       |    Archived = No       |   32 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,32/32] hw/riscv: virt: Simplify virt_{get,set}_aclint() [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 2 - --- 2023-02-07 Alistair Francis New
[PULL,31/32] target/riscv: fix SBI getchar handler for KVM [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,30/32] target/riscv: fix ctzw behavior [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,29/32] target/riscv: fix for virtual instr exception [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,28/32] target/riscv: add a MAINTAINERS entry for XThead* extension support [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,27/32] RISC-V: Adding XTheadFmv ISA extension [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,26/32] RISC-V: Add initial support for T-Head C906 [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,25/32] RISC-V: Set minimum priv version for Zfh to 1.11 [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw 1 - - - --- 2023-02-07 Alistair Francis New
[PULL,24/32] RISC-V: Adding T-Head FMemIdx extension [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,23/32] RISC-V: Adding T-Head MemIdx extension [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,22/32] RISC-V: Adding T-Head MemPair extension [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 2 - --- 2023-02-07 Alistair Francis New
[PULL,21/32] RISC-V: Adding T-Head multiply-accumulate instructions [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,20/32] RISC-V: Adding XTheadCondMov ISA extension [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,19/32] RISC-V: Adding XTheadBs ISA extension [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,18/32] RISC-V: Adding XTheadBb ISA extension [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,17/32] RISC-V: Adding XTheadBa ISA extension [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,16/32] RISC-V: Adding XTheadSync ISA extension [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,15/32] RISC-V: Adding XTheadCmo ISA extension [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,14/32] hw/riscv: change riscv_compute_fdt_addr() semantics [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,13/32] hw/riscv: split fdt address calculation from fdt load [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,12/32] hw/riscv/boot.c: calculate fdt size after fdt_pack() [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,11/32] target/riscv: set tval for triggered watchpoints [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 2 - --- 2023-02-07 Alistair Francis New
[PULL,10/32] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 2 - --- 2023-02-07 Alistair Francis New
[PULL,09/32] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 2 - --- 2023-02-07 Alistair Francis New
[PULL,08/32] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 2 - --- 2023-02-07 Alistair Francis New
[PULL,07/32] target/riscv: Ensure opcode is saved for all relevant instructions [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - 1 1 - --- 2023-02-07 Alistair Francis New
[PULL,06/32] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,05/32] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - 1 1 - --- 2023-02-07 Alistair Francis New
[PULL,04/32] target/riscv: Update VS timer whenever htimedelta changes [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - 1 1 - --- 2023-02-07 Alistair Francis New
[PULL,03/32] hw/riscv: boot: Don't use CSRs if they are disabled [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,02/32] include/hw/riscv/opentitan: update opentitan IRQs [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New
[PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw [PULL,01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-02-07 Alistair Francis New