Show patches with: Series = Adding partial support for 128-bit riscv target       |    State = Action Required       |    Archived = No       |   18 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v5,18/18] target/riscv: actual functions to realize crs 128-bit insns Adding partial support for 128-bit riscv target - - - - --- 2021-11-12 Frédéric Pétrot New
[v5,17/18] target/riscv: modification of the trans_csrxx for 128-bit support Adding partial support for 128-bit riscv target - - 1 - --- 2021-11-12 Frédéric Pétrot New
[v5,16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns Adding partial support for 128-bit riscv target - - 1 - --- 2021-11-12 Frédéric Pétrot New
[v5,15/18] target/riscv: adding high part of some csrs Adding partial support for 128-bit riscv target - - 2 - --- 2021-11-12 Frédéric Pétrot New
[v5,14/18] target/riscv: support for 128-bit M extension Adding partial support for 128-bit riscv target - - 1 - --- 2021-11-12 Frédéric Pétrot New
[v5,13/18] target/riscv: support for 128-bit arithmetic instructions Adding partial support for 128-bit riscv target - - - - --- 2021-11-12 Frédéric Pétrot New
[v5,12/18] target/riscv: support for 128-bit shift instructions Adding partial support for 128-bit riscv target - - - - --- 2021-11-12 Frédéric Pétrot New
[v5,11/18] target/riscv: support for 128-bit U-type instructions Adding partial support for 128-bit riscv target - - 2 - --- 2021-11-12 Frédéric Pétrot New
[v5,10/18] target/riscv: support for 128-bit bitwise instructions Adding partial support for 128-bit riscv target - - 2 - --- 2021-11-12 Frédéric Pétrot New
[v5,09/18] target/riscv: accessors to registers upper part and 128-bit load/store Adding partial support for 128-bit riscv target - - - - --- 2021-11-12 Frédéric Pétrot New
[v5,08/18] target/riscv: moving some insns close to similar insns Adding partial support for 128-bit riscv target - - 2 - --- 2021-11-12 Frédéric Pétrot New
[v5,07/18] target/riscv: setup everything so that riscv128-softmmu compiles Adding partial support for 128-bit riscv target - - - - --- 2021-11-12 Frédéric Pétrot New
[v5,06/18] target/riscv: array for the 64 upper bits of 128-bit registers Adding partial support for 128-bit riscv target - - 1 - --- 2021-11-12 Frédéric Pétrot New
[v5,05/18] target/riscv: separation of bitwise logic and arithmetic helpers Adding partial support for 128-bit riscv target - - 2 - --- 2021-11-12 Frédéric Pétrot New
[v5,04/18] target/riscv: additional macros to check instruction support Adding partial support for 128-bit riscv target - - 2 - --- 2021-11-12 Frédéric Pétrot New
[v5,03/18] qemu/int128: addition of div/rem 128-bit operations Adding partial support for 128-bit riscv target - - 1 - --- 2021-11-12 Frédéric Pétrot New
[v5,02/18] exec/memop: Adding signed quad and octo defines Adding partial support for 128-bit riscv target - - 3 - --- 2021-11-12 Frédéric Pétrot New
[v5,01/18] exec/memop: Adding signedness to quad definitions Adding partial support for 128-bit riscv target - - 2 - --- 2021-11-12 Frédéric Pétrot New