Show patches with: Series = [PULL,v2,01/21] target/riscv: Update the ePMP CSR address       |    State = Action Required       |    Archived = No       |   20 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,v2,21/21] hw/riscv: opentitan: Correct the USB Dev address [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 1 - --- 2021-09-21 Alistair Francis New
[PULL,v2,20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 1 - --- 2021-09-21 Alistair Francis New
[PULL,v2,19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 2 - --- 2021-09-21 Alistair Francis New
[PULL,v2,18/21] docs/system/riscv: sifive_u: Update U-Boot instructions [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 1 - --- 2021-09-21 Alistair Francis New
[PULL,v2,17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 1 2 --- 2021-09-21 Alistair Francis New
[PULL,v2,16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 2 2 --- 2021-09-21 Alistair Francis New
[PULL,v2,15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 1 2 --- 2021-09-21 Alistair Francis New
[PULL,v2,14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 1 2 --- 2021-09-21 Alistair Francis New
[PULL,v2,13/21] hw/riscv: virt: Add optional ACLINT support to virt machine [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 2 - --- 2021-09-21 Alistair Francis New
[PULL,v2,12/21] hw/riscv: virt: Re-factor FDT generation [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 2 - --- 2021-09-21 Alistair Francis New
[PULL,v2,11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 2 - --- 2021-09-21 Alistair Francis New
[PULL,v2,10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 2 - --- 2021-09-21 Alistair Francis New
[PULL,v2,09/21] sifive_u: Connect the SiFive PWM device [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 1 - --- 2021-09-21 Alistair Francis New
[PULL,v2,08/21] hw/timer: Add SiFive PWM support [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 1 - --- 2021-09-21 Alistair Francis New
[PULL,v2,07/21] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 2 - --- 2021-09-21 Alistair Francis New
[PULL,v2,06/21] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 3 1 --- 2021-09-21 Alistair Francis New
[PULL,v2,05/21] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 2 - --- 2021-09-21 Alistair Francis New
[PULL,v2,04/21] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 2 1 --- 2021-09-21 Alistair Francis New
[PULL,v2,02/21] target/riscv: Fix satp write [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 2 - --- 2021-09-21 Alistair Francis New
[PULL,v2,01/21] target/riscv: Update the ePMP CSR address [PULL,v2,01/21] target/riscv: Update the ePMP CSR address - - 1 - --- 2021-09-21 Alistair Francis New