Show patches with: Series = [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB       |    State = Action Required       |    Archived = No       |   18 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,18/18] hw/riscv: microchip_pfsoc: Hook the I2C1 controller [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,17/18] hw/riscv: microchip_pfsoc: Correct DDR memory map [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,16/18] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,15/18] hw/riscv: microchip_pfsoc: Connect the SYSREG module [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,14/18] hw/misc: Add Microchip PolarFire SoC SYSREG module support [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,13/18] hw/riscv: microchip_pfsoc: Connect the IOSCB module [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,12/18] hw/misc: Add Microchip PolarFire SoC IOSCB module support [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,10/18] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,08/18] target/riscv: Add sifive_plic vmstate [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,07/18] target/riscv: Add V extension state description [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 2 - --- 2020-10-29 Alistair Francis New
[PULL,06/18] target/riscv: Add H extension state description [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,05/18] target/riscv: Add PMP state description [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,04/18] target/riscv: Add basic vmstate description of CPU [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,02/18] hw/riscv: virt: Allow passing custom DTB [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New