Show patches with: Series = RISC-V Add the OpenTitan Machine       |    State = Action Required       |    Archived = No       |   11 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v5,11/11] target/riscv: Use a smaller guess size for no-MMU PMP RISC-V Add the OpenTitan Machine - - 1 - --- 2020-05-28 Alistair Francis New
[v5,10/11] riscv/opentitan: Connect the UART device RISC-V Add the OpenTitan Machine - - 2 - --- 2020-05-28 Alistair Francis New
[v5,09/11] riscv/opentitan: Connect the PLIC device RISC-V Add the OpenTitan Machine - - 2 - --- 2020-05-28 Alistair Francis New
[v5,08/11] hw/intc: Initial commit of lowRISC Ibex PLIC RISC-V Add the OpenTitan Machine - - 1 - --- 2020-05-28 Alistair Francis New
[v5,07/11] hw/char: Initial commit of Ibex UART RISC-V Add the OpenTitan Machine - - 2 - --- 2020-05-28 Alistair Francis New
[v5,06/11] riscv: Initial commit of OpenTitan machine RISC-V Add the OpenTitan Machine - - 1 - --- 2020-05-28 Alistair Francis New
[v5,05/11] target/riscv: Add the lowRISC Ibex CPU RISC-V Add the OpenTitan Machine - - 2 - --- 2020-05-28 Alistair Francis New
[v5,04/11] target/riscv: Don't set PMP feature in the cpu init RISC-V Add the OpenTitan Machine - - 1 - --- 2020-05-28 Alistair Francis New
[v5,03/11] target/riscv: Disable the MMU correctly RISC-V Add the OpenTitan Machine - - 1 - --- 2020-05-28 Alistair Francis New
[v5,02/11] target/riscv: Don't overwrite the reset vector RISC-V Add the OpenTitan Machine - - 1 - --- 2020-05-28 Alistair Francis New
[v5,01/11] riscv/boot: Add a missing header include RISC-V Add the OpenTitan Machine - - 2 - --- 2020-05-28 Alistair Francis New