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Add RISC-V Hypervisor Extension v0.5
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| 36 patches
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Apply
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[v1,36/36] target/riscv: Allow enabling the Hypervisor extension
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,33/36] target/riscv: Set htval and mtval2 on execptions
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,32/36] target/riscv: Raise the new execptions when 2nd stage translation fails
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,31/36] target/riscv: Implement second stage MMU
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,30/36] target/riscv: Allow specifying MMU stage
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,29/36] target/riscv: Respect MPRV and SPRV for floating point ops
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,28/36] target/riscv: Mark both sstatus and vsstatus as dirty
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,27/36] target/riscv: Disable guest FP support based on virtual status
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,26/36] target/riscv: Remove the hret instruction
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,25/36] target/riscv: Add hfence instructions
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,24/36] target/riscv: Add Hypervisor trap return support
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,23/36] target/riscv: Add hypvervisor trap support
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,22/36] target/riscv: Generate illegal instruction on WFI when V=1
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,21/36] target/ricsv: Flush the TLB on virtulisation mode changes
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,20/36] target/riscv: Add support for virtual interrupt setting
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,19/36] target/riscv: Extend the SIP CSR to support virtulisation
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,18/36] target/riscv: Extend the MIE CSR to support virtulisation
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,17/36] target/riscv: Set VS bits in mideleg for Hyp extension
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,16/36] target/riscv: Add virtual register swapping function
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,15/36] target/riscv: Convert mstatus to pointers
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,14/36] target/riscv: Add Hypervisor virtual CSRs accesses
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,13/36] target/riscv: Add Hypervisor virtual CSRs accesses
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,12/36] target/riscv: Add Hypervisor CSR access functions
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,11/36] target/riscv: Dump Hypervisor registers if enabled
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,10/36] target/riscv: Print priv and virt in disas log
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,09/36] target/riscv: Fix CSR perm checking for HS mode
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,08/36] target/riscv: Add the force HS exception mode
Add RISC-V Hypervisor Extension v0.5
- - - -
-
-
-
2019-12-09
Alistair Francis
New
[v1,07/36] target/riscv: Add the virtulisation mode
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,06/36] target/riscv: Rename the H irqs to VS irqs
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,05/36] target/riscv: Add support for the new execption numbers
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,04/36] target/riscv: Add the Hypervisor CSRs to CPUState
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,03/36] target/riscv: Add the Hypervisor extension
Add RISC-V Hypervisor Extension v0.5
- - 2 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,02/36] target/riscv: Don't set write permissions on dirty PTEs
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New
[v1,01/36] target/riscv: Convert MIP CSR to target_ulong
Add RISC-V Hypervisor Extension v0.5
- - 1 -
-
-
-
2019-12-09
Alistair Francis
New