Show patches with: Series = Add RISC-V Hypervisor Extension v0.4       |    State = Action Required       |   27 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v1,28/28] target/riscv: Allow enabling the Hypervisor extension Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,25/28] target/riscv: Call the second stage MMU in virtualisation mode Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,24/28] target/riscv: Implement second stage MMU Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,23/28] target/riscv: Allow specifying number of MMU stages Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,22/28] target/riscv: Allow specifying MMU stage Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,21/28] target/riscv: Respect MPRV and SPRV for floating point ops Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,20/28] target/riscv: Mark both sstatus and vsstatus as dirty Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,19/28] target/riscv: Disable guest FP support based on virtual status Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,18/28] target/riscv: Add hfence instructions Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,17/28] target/riscv: Add Hypervisor trap return support Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,16/28] target/riscv: Add hypvervisor trap support Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,15/28] riscv: plic: Always set sip.SEIP bit for HS Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,14/28] target/riscv: Generate illegal instruction on WFI when V=1 Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,13/28] target/ricsv: Flush the TLB on virtulisation mode changes Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,12/28] target/riscv: Add support for virtual interrupt setting Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,11/28] target/riscv: Add background register swapping function Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,10/28] target/riscv: Convert mie and mstatus to pointers Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,09/28] target/riscv: Add Hypervisor virtual CSRs accesses Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,08/28] target/riscv: Add Hypervisor CSR access functions Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,07/28] target/riscv: Dump Hypervisor registers if enabled Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,06/28] target/riscv: Print priv and virt in disas log Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New
[v1,05/28] target/riscv: Add the Hypervisor CSRs to CPUState Add RISC-V Hypervisor Extension v0.4 - - 2 - 0 0 0 2019-08-23 Alistair Francis New
[v1,04/28] target/riscv: Fix CSR perm checking for HS mode Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,03/28] target/riscv: Add the force HS exception mode Add RISC-V Hypervisor Extension v0.4 - - - - 0 0 0 2019-08-23 Alistair Francis New
[v1,01/28] target/riscv: Add the Hypervisor extension Add RISC-V Hypervisor Extension v0.4 - - 1 - 0 0 0 2019-08-23 Alistair Francis New