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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[v1,07/28] tests/tcg: Enable container_cross_cc for microblaze
testing, plugins and gdbstub for 6.2
- - 1 -
-
-
-
2021-10-26
Alex Bennée
New
[v1,06/28] tests/docker: Add debian-microblaze-cross image
testing, plugins and gdbstub for 6.2
- - 2 -
-
-
-
2021-10-26
Alex Bennée
New
[v1,05/28] tests/docker: Add debian-nios2-cross image
testing, plugins and gdbstub for 6.2
- - 2 -
-
-
-
2021-10-26
Alex Bennée
New
[v1,04/28] gitlab-ci: Remove special casing for hexagon testing
testing, plugins and gdbstub for 6.2
- - 2 -
-
-
-
2021-10-26
Alex Bennée
New
[v1,03/28] tests/docker: Update debian-hexagon-cross to a newer toolchain
testing, plugins and gdbstub for 6.2
- - - -
-
-
-
2021-10-26
Alex Bennée
New
[v1,02/28] tests/docker: Simplify debian-all-test-cross
testing, plugins and gdbstub for 6.2
- - - -
-
-
-
2021-10-26
Alex Bennée
New
[v1,01/28] tests/docker: Use apt build-dep in debian10
testing, plugins and gdbstub for 6.2
- - - -
-
-
-
2021-10-26
Alex Bennée
New
hw/i386: fix vmmouse registration
hw/i386: fix vmmouse registration
- - - -
-
-
-
2021-10-26
Pavel Dovgalyuk
New
[v2] hw/arm/virt: Rename default_bus_bypass_iommu
[v2] hw/arm/virt: Rename default_bus_bypass_iommu
- 1 2 1
-
-
-
2021-10-26
Jean-Philippe Brucker
New
block-backend: Silence clang -m32 compiler warning
block-backend: Silence clang -m32 compiler warning
- 1 1 -
-
-
-
2021-10-26
Hanna Czenczek
New
[v2] hvf: arm: Ignore cache operations on MMIO
[v2] hvf: arm: Ignore cache operations on MMIO
- - 4 -
-
-
-
2021-10-26
Alexander Graf
New
[v4,22/22] docs/system: riscv: Document AIA options for virt machine
QEMU RISC-V AIA support
- - 1 -
-
-
-
2021-10-26
Anup Patel
New
[v4,21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,20/22] hw/intc: Add RISC-V AIA IMSIC device emulation
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,18/22] hw/intc: Add RISC-V AIA APLIC device emulation
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,17/22] target/riscv: Allow users to force enable AIA CSRs in HART
QEMU RISC-V AIA support
- - 1 -
-
-
-
2021-10-26
Anup Patel
New
[v4,16/22] hw/riscv: virt: Use AIA INTC compatible string when available
QEMU RISC-V AIA support
- - 1 -
-
-
-
2021-10-26
Anup Patel
New
[v4,15/22] target/riscv: Implement AIA IMSIC interface CSRs
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,14/22] target/riscv: Implement AIA xiselect and xireg CSRs
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,12/22] target/riscv: Implement AIA interrupt filtering CSRs
QEMU RISC-V AIA support
- - 1 -
-
-
-
2021-10-26
Anup Patel
New
[v4,11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,09/22] target/riscv: Implement AIA local interrupt priorities
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,07/22] target/riscv: Add defines for AIA CSRs
QEMU RISC-V AIA support
- - - -
-
-
-
2021-10-26
Anup Patel
New
[v4,06/22] target/riscv: Add AIA cpu feature
QEMU RISC-V AIA support
- - 2 -
-
-
-
2021-10-26
Anup Patel
New
[v4,05/22] target/riscv: Allow setting CPU feature from machine/device emulation
QEMU RISC-V AIA support
- - 2 -
-
-
-
2021-10-26
Anup Patel
New
[v4,04/22] target/riscv: Improve delivery of guest external interrupts
QEMU RISC-V AIA support
- - 1 -
-
-
-
2021-10-26
Anup Patel
New
[v4,03/22] target/riscv: Implement hgeie and hgeip CSRs
QEMU RISC-V AIA support
- - 1 -
-
-
-
2021-10-26
Anup Patel
New
[v4,02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
QEMU RISC-V AIA support
- - 1 -
-
-
-
2021-10-26
Anup Patel
New
[v4,01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
QEMU RISC-V AIA support
- 1 2 -
-
-
-
2021-10-26
Anup Patel
New
[v3,2/2] tests/unit: Add an unit test for smp parsing
hw/core/machine: Add an unit test for smp_parse
- - 1 -
-
-
-
2021-10-26
wangyanan (Y)
New
[v3,1/2] hw/core/machine: Split out the smp parsing code
hw/core/machine: Add an unit test for smp_parse
- - 1 -
-
-
-
2021-10-26
wangyanan (Y)
New
[v5,07/26] riscv: qemu: Add devicetree files for qemu_riscv32/64
fdt: Make OF_BOARD a boolean option
- - - -
-
-
-
2021-10-26
Simon Glass
New
[v5,06/26] arm: qemu: Add a devicetree file for qemu_arm64
fdt: Make OF_BOARD a boolean option
- - - -
-
-
-
2021-10-26
Simon Glass
New
[v5,05/26] arm: qemu: Add a devicetree file for qemu_arm
fdt: Make OF_BOARD a boolean option
- - - -
-
-
-
2021-10-26
Simon Glass
New
[v5,04/26] arm: riscv: qemu: Explain how to extract the generated dt
fdt: Make OF_BOARD a boolean option
- - - -
-
-
-
2021-10-26
Simon Glass
New
[v5,03/26] arm: qemu: Mention -nographic in the docs
fdt: Make OF_BOARD a boolean option
- - - -
-
-
-
2021-10-26
Simon Glass
New
hw/arm/virt: Expose empty NUMA nodes through ACPI
hw/arm/virt: Expose empty NUMA nodes through ACPI
- - 1 -
-
-
-
2021-10-25
Gavin Shan
New
[v3,10/10] hw/riscv: virt: Add PMU DT node to the device tree
Improve PMU support
- - - -
-
-
-
2021-10-25
Atish Patra
New
[v3,09/10] target/riscv: Add few cache related PMU events
Improve PMU support
- - - -
-
-
-
2021-10-25
Atish Patra
New
[v3,08/10] target/riscv: Add sscofpmf extension support
Improve PMU support
- - - -
-
-
-
2021-10-25
Atish Patra
New
[v3,07/10] target/riscv: Support mcycle/minstret write operation
Improve PMU support
- - - -
-
-
-
2021-10-25
Atish Patra
New
[v3,06/10] target/riscv: Add support for hpmcounters/hpmevents
Improve PMU support
- - - -
-
-
-
2021-10-25
Atish Patra
New
[v3,05/10] target/riscv: Implement mcountinhibit CSR
Improve PMU support
- - 2 -
-
-
-
2021-10-25
Atish Patra
New
[v3,04/10] target/riscv: pmu: Make number of counters configurable
Improve PMU support
- - - -
-
-
-
2021-10-25
Atish Patra
New
[v3,03/10] target/riscv: pmu: Rename the counters extension to pmu
Improve PMU support
- - 2 -
-
-
-
2021-10-25
Atish Patra
New
[v3,02/10] target/riscv: Implement PMU CSR predicate function for
Improve PMU support
- - 1 -
-
-
-
2021-10-25
Atish Patra
New
[v3,01/10] target/riscv: Fix PMU CSR predicate function
Improve PMU support
- 1 2 -
-
-
-
2021-10-25
Atish Patra
New
hvf: arm: Ignore cache operations on MMIO
hvf: arm: Ignore cache operations on MMIO
- - 1 -
-
-
-
2021-10-25
Alexander Graf
New
[v4,19/19] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree
target/ppc: DFP instructions using decodetree
- - 2 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,18/19] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree
target/ppc: DFP instructions using decodetree
- - 2 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,17/19] target/ppc: Move dqua[q], drrnd[q] to decodetree
target/ppc: DFP instructions using decodetree
- - 2 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,16/19] target/ppc: Move dquai[q], drint{x, n}[q] to decodetree
target/ppc: DFP instructions using decodetree
- - 2 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,15/19] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,14/19] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree
target/ppc: DFP instructions using decodetree
- - 2 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,13/19] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree
target/ppc: DFP instructions using decodetree
- - 2 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,12/19] target/ppc: Do not update nip on DFP instructions
target/ppc: DFP instructions using decodetree
- - - -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,11/19] target/ppc: Implement DCTFIXQQ
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,10/19] libdecnumber: Introduce decNumberIntegralToInt128
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,09/19] host-utils: Introduce mulu128
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,08/19] target/ppc: Implement DCFFIXQQ
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,07/19] target/ppc: Introduce REQUIRE_FPU
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,06/19] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c
target/ppc: DFP instructions using decodetree
1 - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,05/19] libdecnumber: introduce decNumberFrom[U]Int128
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,04/19] host-utils: add unit tests for divu128/divs128
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,03/19] host-utils: add 128-bit quotient support to divu128/divs128
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,02/19] host-utils: move udiv_qrnnd() to host-utils
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v4,01/19] host-utils: move checks out of divu128/divs128
target/ppc: DFP instructions using decodetree
- - 1 -
-
-
-
2021-10-25
Luis Fernando Fujita Pires
New
[v17,8/8] target/riscv: Allow experimental J-ext to be turned on
RISC-V Pointer Masking implementation
- - 3 -
-
-
-
2021-10-25
Alexey Baturo
New
[v17,7/8] target/riscv: Implement address masking functions required for RISC-V Pointer Masking ext…
RISC-V Pointer Masking implementation
- - 2 -
-
-
-
2021-10-25
Alexey Baturo
New
[v17,6/8] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
RISC-V Pointer Masking implementation
- - 2 -
-
-
-
2021-10-25
Alexey Baturo
New
[v17,5/8] target/riscv: Print new PM CSRs in QEMU logs
RISC-V Pointer Masking implementation
- - 1 -
-
-
-
2021-10-25
Alexey Baturo
New
[v17,4/8] target/riscv: Add J extension state description
RISC-V Pointer Masking implementation
- - 1 -
-
-
-
2021-10-25
Alexey Baturo
New
[v17,3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
RISC-V Pointer Masking implementation
- - 1 -
-
-
-
2021-10-25
Alexey Baturo
New
[v17,2/8] target/riscv: Add CSR defines for RISC-V PM extension
RISC-V Pointer Masking implementation
- - 1 -
-
-
-
2021-10-25
Alexey Baturo
New
[v17,1/8] target/riscv: Add J-extension into RISC-V
RISC-V Pointer Masking implementation
- - 3 -
-
-
-
2021-10-25
Alexey Baturo
New
[v5] isa-applesmc: provide OSK forwarding on Apple hosts
[v5] isa-applesmc: provide OSK forwarding on Apple hosts
- - - -
-
-
-
2021-10-25
Vladislav Yaroshchuk
New
[RFC,2/2] util/async: replace __thread with QEMU TLS macros
tls: add macros for coroutine-safe TLS variables
- - - -
-
-
-
2021-10-25
Stefan Hajnoczi
New
[RFC,1/2] tls: add macros for coroutine-safe TLS variables
tls: add macros for coroutine-safe TLS variables
- - - -
-
-
-
2021-10-25
Stefan Hajnoczi
New
[v2] hvf: Avoid mapping regions < PAGE_SIZE as ram
[v2] hvf: Avoid mapping regions < PAGE_SIZE as ram
- - 1 -
-
-
-
2021-10-25
Alexander Graf
New
[v2,2/2] target/riscv: csr: Implement mconfigptr CSR
mconfigptr support
- - - -
-
-
-
2021-10-25
Rahul Pathak
New
[v2,1/2] target/riscv: Add priv spec 1.12.0 version check
mconfigptr support
- - - -
-
-
-
2021-10-25
Rahul Pathak
New
[v4,17/17] target/riscv: actual functions to realize crs 128-bit insns
Adding partial support for 128-bit riscv target
- - - -
-
-
-
2021-10-25
Frédéric Pétrot
New
[v4,16/17] target/riscv: modification of the trans_csrxx for 128-bit support
Adding partial support for 128-bit riscv target
- - 1 -
-
-
-
2021-10-25
Frédéric Pétrot
New
[v4,15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns
Adding partial support for 128-bit riscv target
- - 1 -
-
-
-
2021-10-25
Frédéric Pétrot
New
[v4,14/17] target/riscv: adding high part of some csrs
Adding partial support for 128-bit riscv target
- - 1 -
-
-
-
2021-10-25
Frédéric Pétrot
New
[v4,13/17] target/riscv: support for 128-bit M extension
Adding partial support for 128-bit riscv target
- - 1 -
-
-
-
2021-10-25
Frédéric Pétrot
New
[v4,12/17] target/riscv: support for 128-bit arithmetic instructions
Adding partial support for 128-bit riscv target
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2021-10-25
Frédéric Pétrot
New
[v4,11/17] target/riscv: support for 128-bit shift instructions
Adding partial support for 128-bit riscv target
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2021-10-25
Frédéric Pétrot
New
[v4,10/17] target/riscv: support for 128-bit U-type instructions
Adding partial support for 128-bit riscv target
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2021-10-25
Frédéric Pétrot
New
[v4,09/17] target/riscv: support for 128-bit bitwise instructions
Adding partial support for 128-bit riscv target
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2021-10-25
Frédéric Pétrot
New
[v4,08/17] target/riscv: accessors to registers upper part and 128-bit load/store
Adding partial support for 128-bit riscv target
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2021-10-25
Frédéric Pétrot
New
[v4,07/17] target/riscv: moving some insns close to similar insns
Adding partial support for 128-bit riscv target
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2021-10-25
Frédéric Pétrot
New
[v4,06/17] target/riscv: setup everything so that riscv128-softmmu compiles
Adding partial support for 128-bit riscv target
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2021-10-25
Frédéric Pétrot
New
[v4,05/17] target/riscv: array for the 64 upper bits of 128-bit registers
Adding partial support for 128-bit riscv target
- - 1 -
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2021-10-25
Frédéric Pétrot
New
[v4,04/17] target/riscv: separation of bitwise logic and aritmetic helpers
Adding partial support for 128-bit riscv target
- - 2 -
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2021-10-25
Frédéric Pétrot
New
[v4,03/17] target/riscv: additional macros to check instruction support
Adding partial support for 128-bit riscv target
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2021-10-25
Frédéric Pétrot
New
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