Show patches with: State = Action Required       |    Archived = No       |   426981 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[2/2] target/i386: cmpxchg only overwrites ZF target/i386: two fixes for cmpxchg - - - - --- 2022-09-11 Paolo Bonzini New
[2/2] target/i386: fix IEEE SSE floating-point exception raising target/i386: SSE floating-point fixes - - - - --- 2020-06-25 Joseph Myers New
[2/2] target/i386: fix IEEE x87 floating-point exception raising target/i386: x87 exceptions fixes - - - - --- 2020-05-15 Joseph Myers New
[2/2] target/i386: fix memory operand size for CVTPS2PD target/i386: reimplement fp2fp conversion instructions - - 1 - --- 2023-08-29 Paolo Bonzini New
[2/2] target/i386: ignore CPL0-specific features in user mode emulation target/i386: allow using named CPU modeles with user mode emulation - 2 - - --- 2023-06-18 Paolo Bonzini New
[2/2] target/i386: kvm: Init nested-state in case of vCPU exposed with SVM target/i386: kvm: Fix treatment of AMD SVM in nested migration - - 2 - --- 2019-06-21 Liran Alon New
[2/2] target/i386: sev: Do not pin the ram device memory region Fix SEV VM device assignment - 1 - - --- 2019-01-17 Brijesh Singh New
[2/2] target/i386: trap on instructions longer than >15 bytes target/i386: trap on instructions longer than >15 bytes - - 1 - --- 2017-10-12 Paolo Bonzini New
[2/2] target/lm32: hold BQL in gdbstub BQL patches for the lm32 target - - - - --- 2018-05-21 Michael Walle New
[2/2] target/loongarch: Fix raise_mmu_exception() set wrong exception_index [1/2] target/loongarch: Add exception subcode - - 1 - --- 2022-11-01 gaosong New
[2/2] target/loongarch: Fix return value of CHECK_FPE [1/2] target/loongarch: Separate the hardware flags into MMU index and PLV - 1 1 - --- 2022-11-07 Rui Wang New
[2/2] target/m68k: Add vmstate definition for M68kCPU [1/2] target/m68k: remove useless qregs array - - - - --- 2020-10-22 Laurent Vivier New
[2/2] target/m68k: Enable halt insn for 68060 target/m68k: Enable halt insn for 68060 - - 1 - --- 2022-04-30 Richard Henderson New
[2/2] target/m68k: Fix bug in semihosted exit handling Fix bug in nios2 and m68k semihosting - 1 2 - --- 2019-08-21 Sandra Loosemore New
[2/2] target/m68k: Perform writback before modifying SR target/m68k: fix two writes to %sr - - 2 - --- 2022-09-13 Richard Henderson New
[2/2] target/m68k: Remove sprintf() calls m68k: Remove sprintf() calls due to macOS deprecation - - 1 - --- 2024-04-11 Philippe Mathieu-Daudé New
[2/2] target/m68k: add M68K_FEATURE_NO_DALIGN feature target/m68k: MacOS related fixes - - 1 - --- 2021-03-07 Mark Cave-Ayland New
[2/2] target/m68k: fix gdb for m68xxx m68k fpu fixes - - 1 - --- 2020-04-28 KONRAD Frederic New
[2/2] target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr privilege check target/m68k: MacOS supervisor/user mode switch fixes - part 2 - - 1 - --- 2022-09-25 Mark Cave-Ayland New
[2/2] target/mips/kvm: Assert unreachable code is not used mips: Minor simplifications for KVM use 1 - 1 - --- 2020-04-29 Philippe Mathieu-Daudé New
[2/2] target/mips: Add definition of Loongson-3A3000 CPU [1/2] target/mips: Coding style update to fix checkpatch errors - - - - --- 2020-08-13 Kaige Li New
[2/2] target/mips: Add entries for the Toshiba's R3900 and R5900 cores mips: Allow more 'Chip specific instructions' flags - - - - --- 2018-09-09 Philippe Mathieu-Daudé New
[2/2] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr - 1 1 - --- 2021-08-13 Philippe Mathieu-Daudé New
[2/2] target/mips: Correct check for CABS instructions [1/2] target/mips: Don't check COP1X for 64 bit FP mode - - - - --- 2022-11-02 Jiaxun Yang New
[2/2] target/mips: Correct data on deprecated r4k machine target/mips: Misc MIPS fixes and improvements for 5.0 - 1 2 - --- 2019-12-19 Aleksandar Markovic New
[2/2] target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1 target/mips: Fix decoding mechanisms of R5900 M{F, T}{HI, LO}1 and DIV[U]1 - 1 1 - --- 2018-11-02 Fredrik Noring New
[2/2] target/mips: Fix decoding of ALIGN and DALIGN instructions target/mips: Two corrections - - 1 - --- 2018-10-22 Aleksandar Markovic New
[2/2] target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument target/mips: Let cpu_supports_isa() take CPUMIPSState argument - - - - --- 2020-12-07 Philippe Mathieu-Daudé New
[2/2] target/mips: MOD_<U|S>.<B|H|W|D> MSA insturctions fixed target/mips: Integer division by zero in MSA insturctions - - - - --- 2019-04-01 Mateja Marjanovic New
[2/2] target/mips: Merge msa32/msa64 decodetree definitions target/mips: Simplify MSA decodetree - - 1 - --- 2021-06-17 Philippe Mathieu-Daudé New
[2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions target/mips: Optimize MSA ILVEV and ILVOD instructions - - - - --- 2019-03-19 Mateja Marjanovic New
[2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions target/mips: Optimize ILVEV and ILVOD MSA instructions - - - - --- 2019-03-15 Mateja Marjanovic New
[2/2] target/mips: Rearrange vector compare less than (signed) instructions target/mips: Rearrange handling of vector compare instructions - - 1 - --- 2019-10-23 Filip Bozuta New
[2/2] target/mips: Tests for binary integer MSA instruction (add, adds, hadd...) target/mips: Improve performance for MSA binary operations - - 1 - --- 2019-03-04 Mateja Marjanovic New
[2/2] target/nios2: Move nios2_check_interrupts() into target/nios2 target/nios2: Roll cpu_pic code into CPU itself - - 1 - --- 2020-11-27 Peter Maydell New
[2/2] target/nios2: Use MMUAccessType enum type when possible target/nios2: Pass MMUAccessType to mmu_translate() - - 1 - --- 2021-01-27 Philippe Mathieu-Daudé New
[2/2] target/openrisc: Implement EPH bit 1 - - - --- 2017-04-18 Tim 'mithro' Ansell New
[2/2] target/openrisc: convert to TranslatorOps Untitled series #29200 - - - - --- 2018-02-18 Emilio Cota New
[2/2] target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition Small clean up in target/ppc/cpu.h - - - - --- 2020-02-16 BALATON Zoltan New
[2/2] target/ppc/kvm: Convert DPRINTF to traces [1/2] target/ppc/trace-events: Fix trivial typo - - - - --- 2019-04-05 Greg Kurz New
[2/2] target/ppc/kvm: Use KVM_CAP_PPC_AIL_MODE_3 to determine cap-ail-mode-3 support [1/2] spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcall - - - - --- 2022-02-14 Nicholas Piggin New
[2/2] target/ppc: Add POWER10 exception model ppc: rework AIL logic, add POWER10 exception model - - 1 1 --- 2021-05-01 Nicholas Piggin New
[2/2] target/ppc: Add TFMR SPR implementation with read and write helpers target/ppc: Easy parts of the POWER chiptod series - - 1 - --- 2023-06-25 Nicholas Piggin New
[2/2] target/ppc: Bugfix FP when OE/UE are set Floating-point OE/UE exception bug - - 1 - --- 2022-08-05 Lucas Mateus Martins Araujo e Castro New
[2/2] target/ppc: Check DEXCR on hash{st, chk} instructions target/ppc: Implement Dynamic Execution Control Registers - - 1 - --- 2022-11-24 Nicholas Miehlbradt New
[2/2] target/ppc: Check privilege level based on PSR and LPCR[HR] in tlbie[l] Require hypervisor privilege for tlbie[l] when PSR=0 and HR=1. - - - - --- 2021-09-09 Matheus K. Ferst New
[2/2] target/ppc: Drop PowerPCCPUClass::interrupts_big_endian() target/ppc: Drop PowerPCCPUClass::interrupts_big_endian() - - 1 - --- 2021-06-22 Greg Kurz New
[2/2] target/ppc: Fix FPSCR.FI changing in float_overflow_excp() target/ppc: Fix FPSCR.FI bit - - - - --- 2022-05-09 Víctor Colombo New
[2/2] target/ppc: Fix GDB register indexing on secondary CPUs [1/2] target/ppc: Restore [H]DEXCR to 64-bits - 1 1 - --- 2024-03-20 Benjamin Gray New
[2/2] target/ppc: Fix ISA v3.0 (POWER9) slbia implementation [1/2] target/ppc: Fix slbia TLB invalidation gap - - - - --- 2020-03-18 Nicholas Piggin New
[2/2] target/ppc: Fix VRMA page size for ISA v3.0 target/ppc: Fixes for hash MMU for ISA v3.0 - - - - --- 2023-07-21 Nicholas Piggin New
[2/2] target/ppc: Fix compilation with FLUSH_ALL_TLBS debug option target/ppc: MMU debug fixes - 1 - - --- 2021-07-02 Fabiano Rosas New
[2/2] target/ppc: Introduce an mmu_is_64bit() helper target/ppc: Fix detection of 64-bit MMU models - - - - --- 2020-12-09 Greg Kurz New
[2/2] target/ppc: Optimize x[sv]xsigdp using deposit_i64() target/ppc: Optimize VSX instructions using deposit_i64() - - - - --- 2019-03-09 Philippe Mathieu-Daudé New
[2/2] target/ppc: Reduce the size of ppc_spr_t target/ppc: Clean up _spr_register - - - - --- 2021-05-01 Richard Henderson New
[2/2] target/ppc: Use tcg_constant_i64() in gen_brh() target/ppc: Use tcg_constant_* - - 1 - --- 2021-10-03 Philippe Mathieu-Daudé New
[2/2] target/ppc: Use tcg_gen_gvec_bitsel target/ppc: make use of new gvec expanders - - - - --- 2019-05-18 Richard Henderson New
[2/2] target/ppc: add support for Hypervisor Facility Unavailable Exception ppc: add support for Directed Privileged Doorbell (non-hypervisor) - - - - --- 2020-01-09 Cédric Le Goater New
[2/2] target/ppc: convert to TranslatorOps target/ppc: convert to generic translation loop - - 1 - --- 2018-02-15 Emilio Cota New
[2/2] target/ppc: fix vextu[bhw][lr]x helpers target/ppc: Fix vextu[bhw][lr]x on big endian hosts - 1 1 - --- 2021-08-24 Matheus K. Ferst New
[2/2] target/ppc: ppc_store_fpscr doesn't update bit 52 Fix mtfsf, mtfsfi and mtfsb1 bug - - - - --- 2021-10-20 Lucas Mateus Martins Araujo e Castro New
[2/2] target/riscv/cpu.c: add smepmp isa string target/riscv: add missing riscv,isa strings - - 2 - --- 2023-07-20 Daniel Henrique Barboza New
[2/2] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next - - 2 - --- 2023-01-10 Daniel Henrique Barboza New
[2/2] target/riscv/cpu_helper.c: Fix mxr bit behavior Fix mmu translation with H extension - 1 1 - --- 2023-11-20 Ivan Klokov New
[2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS [1/2] target/riscv/csr.c: Add functional of hvictl CSR - - - - --- 2024-02-12 Irina Ryapolova New
[2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS [1/2] target/riscv/csr.c: Add functional of hvictl CSR - - 1 - --- 2024-02-12 Irina Ryapolova New
[2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Added the ability to delegate LCOFI to VS - - 1 - --- 2023-12-21 Vadim Shakirov New
[2/2] target/riscv/kvm: support KVM_GET_REG_LIST riscv, kvm: support KVM_GET_REG_LIST - - - - --- 2023-10-03 Daniel Henrique Barboza New
[2/2] target/riscv/kvm: update KVM exts to Linux 6.8 target/riscv/kvm: update KVM exts to Linux 6.8 1 - - - --- 2024-03-04 Daniel Henrique Barboza New
[2/2] target/riscv/pmp.c: Fix the index offset on RV64 Fix some PMP implementation - - - - --- 2020-07-20 Zong Li New
[2/2] target/riscv/tcg-cpu.c: add extension properties for all cpus riscv: add extension properties for all cpus - - 1 - --- 2023-09-26 Daniel Henrique Barboza New
[2/2] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig target/riscv: some vector_helper.c cleanups - - 2 - --- 2023-02-26 Daniel Henrique Barboza New
[2/2] target/riscv/vector_helper.c: make vext_set_tail_elems_1s() debug only target/riscv: RVV 1-fill tail element changes - - - - --- 2023-04-27 Daniel Henrique Barboza New
[2/2] target/riscv: Add a sifive-e34 cpu type Support different CPU types for the sifive_e machine - - - - --- 2020-03-13 Corey Wharton New
[2/2] target/riscv: Add a sifive-e34 cpu type Support different CPU types for the sifive_e machine - - - - --- 2020-03-13 Corey Wharton New
[2/2] target/riscv: Add checks for several RVC reserved operands target/riscv fixup and reserved argument checks - - - - --- 2019-04-25 Richard Henderson New
[2/2] target/riscv: Add ext_z*_enabled for implicitly enabled extensions target/riscv: Separate implicitly-enabled and explicitly-enabled extensions - - - - --- 2023-04-10 Weiwei Li New
[2/2] target/riscv: Add short-isa-string option target/riscv: ISA string conversion fix and enhancement - - - - --- 2022-04-24 Tsukasa OI New
[2/2] target/riscv: Allow software access to MIP SEIP target/riscv: Allow software access to MIP SEIP - - 1 - --- 2022-03-15 Alistair Francis New
[2/2] target/riscv: Auto set elen from vector extension by default [1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN - - - - --- 2022-07-08 Kito Cheng New
[2/2] target/riscv: Call check_access() before tcg_temp_new() [1/2] target/riscv: Reduce duplicated code in trans_rvh.c.inc - - - - --- 2021-02-19 Alex Richardson New
[2/2] target/riscv: Check 'A' and split extensions for atomic instructions target/riscv: Add support for Zaamo & Zalrsc - - - - --- 2024-01-15 Rob Bradford New
[2/2] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ [1/2] target/riscv: Simplify helper_sret() a little bit - - 1 - --- 2022-12-07 Bin Meng New
[2/2] target/riscv: Do amo*.w insns operate with 32 bits target/riscv: fixup atomic implementation - - - - --- 2020-06-29 LIU Zhiwei New
[2/2] target/riscv: Fix sfence.vm/a both available in any priv version target/riscv: Bugfixes found in decodetree conversion - - 2 - --- 2018-11-08 Bastian Koppelmann New
[2/2] target/riscv: Ibex: Support priv version 1.11 target/riscv: Fixes for Ibex and OpenTitan - - 1 - --- 2022-06-29 Alistair Francis New
[2/2] target/riscv: Implement dump content of vector register [1/2] util/log: Add vu to dump content of vector unit - - - - --- 2022-07-08 Kito Cheng New
[2/2] target/riscv: Implement the stval/mtval illegal instruction RISC-V: Populate mtval and stval - - - - --- 2021-12-10 Alistair Francis New
[2/2] target/riscv: Legalize MPP value in write_mstatus target/riscv: Fix mstatus.MPP related support - - - - --- 2023-03-30 Weiwei Li New
[2/2] target/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) hw/riscv: Make CPU config error handling generous - - - - --- 2022-05-13 Tsukasa OI New
[2/2] target/riscv: Make the "virt" register writable by GDB [1/2] target/riscv: Expose "virt" register for GDB for reads - - 2 - --- 2023-03-05 Jim Shu New
[2/2] target/riscv: Mark MSTATUS_FS dirty RISC-V: Mark FP status dirty - - 1 1 --- 2018-03-28 Richard Henderson New
[2/2] target/riscv: Mark amo insns during translation target/riscv: Annotate atomic operations - - 1 - --- 2022-04-01 Richard Henderson New
[2/2] target/riscv: Only build KVM guest with same wordsize as host target/riscv: Only build qemu-system-riscv$$ on rv$$ host - - - - --- 2023-06-27 Philippe Mathieu-Daudé New
[2/2] target/riscv: Optimize ambiguous local variable in pmp_hart_has_privs [1/2] target/riscv: Remove redundant check in pmp_is_locked - - - - --- 2023-06-28 Ruibo Lu New
[2/2] target/riscv: Raise an exception when sdtrig is turned off Export debug triggers as an extension - - - - --- 2024-01-10 Himanshu Chauhan New
[2/2] target/riscv: Remove helper_set_rod_rounding_mode target/riscv: Fix double calls to gen_set_rm [#1411] - - 2 - --- 2023-01-15 Richard Henderson New
[2/2] target/riscv: Run extension checks for all CPUs target/riscv: Cleanup exposed CPU properties - - - - --- 2022-05-17 Alistair Francis New
[2/2] target/riscv: Support xtheadmaee for thead-c906 target/riscv: Support mxstatus CSR for thead-c906 - - - - --- 2024-01-30 LIU Zhiwei New
[2/2] target/riscv: The whole vector register move instructions depend on vsew Make vector whole-register move (vmv) depend on vtype register 1 - - - --- 2023-11-29 Max Chou New
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