Show patches with: State = Action Required       |    Archived = No       |   431544 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v2] cpus: Move CPU code from exec.c to cpus-common.c [v2] cpus: Move CPU code from exec.c to cpus-common.c - - 2 - --- 2020-07-02 Philippe Mathieu-Daudé New
linux-user: Fix "print_fdset()" in "strace.c" to not print ", " after last value linux-user: Fix "print_fdset()" in "strace.c" to not print ", " after last value - - 1 - --- 2020-07-02 Filip Bozuta New
[2/2] configure: add support for Control-Flow Integrity Add support for Control-Flow Integrity - - - - --- 2020-07-02 Daniele Buono New
[1/2] check-block: enable iotests with cfi-icall Add support for Control-Flow Integrity - - - - --- 2020-07-02 Daniele Buono New
MAINTAINERS: Remove myself from FPU emulation maintenance MAINTAINERS: Remove myself from FPU emulation maintenance - - 1 - --- 2020-07-02 Aurelien Jarno New
[v4,11/11] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions Add several Power ISA 3.1 32/64-bit vector instructions - - - - --- 2020-07-01 Lijun Pan New
[v4,10/11] target/ppc: add vmulh{su}d instructions Add several Power ISA 3.1 32/64-bit vector instructions - - 1 - --- 2020-07-01 Lijun Pan New
[v4,09/11] fix the prototype of muls64/mulu64 Add several Power ISA 3.1 32/64-bit vector instructions - - 1 - --- 2020-07-01 Lijun Pan New
[v4,08/11] target/ppc: add vmulh{su}w instructions Add several Power ISA 3.1 32/64-bit vector instructions - - 1 - --- 2020-07-01 Lijun Pan New
[v4,07/11] target/ppc: add vmulld to INDEX_op_mul_vec case Add several Power ISA 3.1 32/64-bit vector instructions - - - - --- 2020-07-01 Lijun Pan New
[v4,06/11] Update PowerPC AT_HWCAP2 definition Add several Power ISA 3.1 32/64-bit vector instructions - - - - --- 2020-07-01 Lijun Pan New
[v4,05/11] target/ppc: add vmulld instruction Add several Power ISA 3.1 32/64-bit vector instructions - - - - --- 2020-07-01 Lijun Pan New
[v4,04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul Add several Power ISA 3.1 32/64-bit vector instructions - - 1 - --- 2020-07-01 Lijun Pan New
[v4,03/11] target/ppc: add byte-reverse br[dwh] instructions Add several Power ISA 3.1 32/64-bit vector instructions - - - - --- 2020-07-01 Lijun Pan New
[v4,02/11] target/ppc: Enable Power ISA 3.1 Add several Power ISA 3.1 32/64-bit vector instructions - - - - --- 2020-07-01 Lijun Pan New
[v4,01/11] target/ppc: Introduce Power ISA 3.1 flag Add several Power ISA 3.1 32/64-bit vector instructions - - - - --- 2020-07-01 Lijun Pan New
[v4,2/2] nvme: allow cmb and pmr to be enabled on same device [v4,1/2] nvme: indicate CMB support through controller capabilities register - - - - --- 2020-07-01 Andrzej Jakowski New
[v4,1/2] nvme: indicate CMB support through controller capabilities register [v4,1/2] nvme: indicate CMB support through controller capabilities register - - 2 - --- 2020-07-01 Andrzej Jakowski New
[v4,2/2] target/m68k: consolidate physical translation offset into get_physical_address() target/m68k: fix physical address translation in m68k_cpu_get_phys_page_debug() - - 1 - --- 2020-07-01 Mark Cave-Ayland New
[v4,1/2] target/m68k: fix physical address translation in m68k_cpu_get_phys_page_debug() target/m68k: fix physical address translation in m68k_cpu_get_phys_page_debug() - 1 2 - --- 2020-07-01 Mark Cave-Ayland New
target/arm: Treat unknown SMC calls as NOP target/arm: Treat unknown SMC calls as NOP - - - - --- 2020-07-01 Alexander Graf New
[v3,2/2] net: detect errors from probing vnet hdr flag for TAP devices net: tap: check file descriptor can be used - - 1 1 --- 2020-07-01 Laurent Vivier New
[v3,1/2] net: tap: check if the file descriptor is valid before using it net: tap: check file descriptor can be used - - 2 - --- 2020-07-01 Laurent Vivier New
[v4,4/4] RISC-V: Support 64 bit start address [v4,1/4] riscv: Unify Qemu's reset vector code path - - 2 1 --- 2020-07-01 Atish Patra New
[v4,3/4] riscv: Add opensbi firmware dynamic support [v4,1/4] riscv: Unify Qemu's reset vector code path - - 2 1 --- 2020-07-01 Atish Patra New
[v4,2/4] RISC-V: Copy the fdt in dram instead of ROM [v4,1/4] riscv: Unify Qemu's reset vector code path - - 2 1 --- 2020-07-01 Atish Patra New
[v4,1/4] riscv: Unify Qemu's reset vector code path [v4,1/4] riscv: Unify Qemu's reset vector code path - - 2 1 --- 2020-07-01 Atish Patra New
[v3,2/2] MAINTAINERS: Adjust MIPS maintainership target mips: Misc fixes and improvements - - - - --- 2020-07-01 Aleksandar Markovic New
[v3,1/2] target/mips: Remove identical if/else branches target mips: Misc fixes and improvements - 1 - - --- 2020-07-01 Aleksandar Markovic New
[RFC] cpus: Initialize current_cpu with the first vCPU created [RFC] cpus: Initialize current_cpu with the first vCPU created - - - - --- 2020-07-01 Philippe Mathieu-Daudé New
ui: fix vc_chr_write call in text_console_do_init ui: fix vc_chr_write call in text_console_do_init - - - - --- 2020-07-01 Gerd Hoffmann New
util/drm: make portable util/drm: make portable - - 1 - --- 2020-07-01 Gerd Hoffmann New
cpus: Move CPU code from exec.c to cpus.c cpus: Move CPU code from exec.c to cpus.c - - 2 - --- 2020-07-01 Philippe Mathieu-Daudé New
[v2,3/3] hw/386: Fix uninitialized memory with -device and CPU hotplug Fix couple of issues with AMD topology - 1 - - --- 2020-07-01 Babu Moger New
[v2,2/3] hw/i386: Build apic_id from CpuInstanceProperties Fix couple of issues with AMD topology - - - - --- 2020-07-01 Babu Moger New
[v2,1/3] hw/i386: Initialize topo_ids from CpuInstanceProperties Fix couple of issues with AMD topology - - - - --- 2020-07-01 Babu Moger New
tcg: Fix do_nonatomic_op_* vs signed operations tcg: Fix do_nonatomic_op_* vs signed operations - - 2 - --- 2020-07-01 Richard Henderson New
[Bug,1878645] Re: [PATCH v4 01/40] hw/isa: check for current_cpu before generating IRQ [Bug,1878645] Re: [PATCH v4 01/40] hw/isa: check for current_cpu before generating IRQ - - - - --- 2020-07-01 Philippe Mathieu-Daudé New
[v2,3/3] docs/devel: add some notes on tcg-icount for developers some docs (booting, mttcg, icount) - - 1 - --- 2020-07-01 Alex Bennée New
[v2,2/3] docs/devel: convert and update MTTCG design document some docs (booting, mttcg, icount) - - 1 - --- 2020-07-01 Alex Bennée New
[v2,1/3] docs/booting.rst: start documenting the boot process some docs (booting, mttcg, icount) - - 1 - --- 2020-07-01 Alex Bennée New
[3/3] block: switch to use qemu_open_err for improved errors block: improve error reporting for unsupported O_DIRECT - - - - --- 2020-07-01 Daniel P. Berrangé New
[2/3] util: support detailed error reporting for qemu_open block: improve error reporting for unsupported O_DIRECT - - - - --- 2020-07-01 Daniel P. Berrangé New
[1/3] util: validate whether O_DIRECT is supported after failure block: improve error reporting for unsupported O_DIRECT - - 1 - --- 2020-07-01 Daniel P. Berrangé New
[v12,61/61] target/riscv: configure and turn on vector extension from command line target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,60/61] target/riscv: vector compress instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,59/61] target/riscv: vector register gather instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,58/61] target/riscv: vector slide instructions target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,57/61] target/riscv: floating-point scalar move instructions target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,56/61] target/riscv: integer scalar move instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,55/61] target/riscv: integer extract instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,54/61] target/riscv: vector element index instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,53/61] target/riscv: vector iota instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,52/61] target/riscv: set-X-first mask bit target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,51/61] target/riscv: vmfirst find-first-set mask bit target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,50/61] target/riscv: vector mask population count vmpopc target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,49/61] target/riscv: vector mask-register logical instructions target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,48/61] target/riscv: vector widening floating-point reduction instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,47/61] target/riscv: vector single-width floating-point reduction instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,46/61] target/riscv: vector wideing integer reduction instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,45/61] target/riscv: vector single-width integer reduction instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,44/61] target/riscv: narrowing floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,43/61] target/riscv: widening floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,42/61] target/riscv: vector floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,41/61] target/riscv: vector floating-point merge instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,40/61] target/riscv: vector floating-point classify instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,39/61] target/riscv: vector floating-point compare instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,38/61] target/riscv: vector floating-point sign-injection instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,37/61] target/riscv: vector floating-point min/max instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,36/61] target/riscv: vector floating-point square-root instruction target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,35/61] target/riscv: vector widening floating-point fused multiply-add instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,34/61] target/riscv: vector single-width floating-point fused multiply-add instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,33/61] target/riscv: vector widening floating-point multiply target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,32/61] target/riscv: vector single-width floating-point multiply/divide instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,31/61] target/riscv: vector widening floating-point add/subtract instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,30/61] target/riscv: vector single-width floating-point add/subtract instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,29/61] target/riscv: vector narrowing fixed-point clip instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,28/61] target/riscv: vector single-width scaling shift instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,27/61] target/riscv: vector widening saturating scaled multiply-add target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,26/61] target/riscv: vector single-width fractional multiply with rounding and saturation target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,25/61] target/riscv: vector single-width averaging add and subtract target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,24/61] target/riscv: vector single-width saturating add and subtract target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,23/61] target/riscv: vector integer merge and move instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,22/61] target/riscv: vector widening integer multiply-add instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,21/61] target/riscv: vector single-width integer multiply-add instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,20/61] target/riscv: vector widening integer multiply instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,19/61] target/riscv: vector integer divide instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,18/61] target/riscv: vector single-width integer multiply instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,17/61] target/riscv: vector integer min/max instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,16/61] target/riscv: vector integer comparison instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,15/61] target/riscv: vector narrowing integer right shift instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,14/61] target/riscv: vector single-width bit shift instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,13/61] target/riscv: vector bitwise logical instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,11/61] target/riscv: vector widening integer add and subtract target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,10/61] target/riscv: vector single-width integer add and subtract target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,09/61] target/riscv: add vector amo operations target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,08/61] target/riscv: add fault-only-first unit stride load target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,07/61] target/riscv: add vector index load and store instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,06/61] target/riscv: add vector stride load and store instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
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