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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[5/5] hw/intc/arm_gic: Actually set the active bits for active interrupts
- - - -
-
-
-
2015-07-28
Peter Maydell
New
hw/pci-host/bonito: Avoid buffer overrun for bad LDMA/COP accesses
1 - - -
-
-
-
2015-07-30
Peter Maydell
New
[1/4] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
- - 1 -
-
-
-
2015-07-30
Peter Maydell
New
[2/4] target-arm: Implement missing AMAIR registers
- - 1 -
-
-
-
2015-07-30
Peter Maydell
New
[3/4] target-arm: Implement missing AFSR registers
- - 1 -
-
-
-
2015-07-30
Peter Maydell
New
[4/4] target-arm: Implement missing ACTLR registers
- - 1 -
-
-
-
2015-07-30
Peter Maydell
New
[1/6] cputlb: Add functions for flushing TLB for a single MMU index
- - - -
-
-
-
2015-08-07
Peter Maydell
New
[2/6] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
- - - -
-
-
-
2015-08-07
Peter Maydell
New
[3/6] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
- - - -
-
-
-
2015-08-07
Peter Maydell
New
[4/6] target-arm: Implement missing EL2 TLBI operations
- - - -
-
-
-
2015-08-07
Peter Maydell
New
[5/6] target-arm: Implement missing EL3 TLB invalidate operations
- - - -
-
-
-
2015-08-07
Peter Maydell
New
[6/6] target-arm: Implement AArch64 TLBI operations on IPAs
- - - -
-
-
-
2015-08-07
Peter Maydell
New
[v2] target-cris: update CPU state save/load to use VMStateDescription
1 - - -
-
-
-
2015-08-07
Peter Maydell
New
[1/4] vmstate: introduce CPU_DoubleU arrays
- - - -
-
-
-
2015-08-10
Peter Maydell
New
[2/4] target-sparc: Split cpu_put_psr into side-effect and no-side-effect parts
- - - -
-
-
-
2015-08-10
Peter Maydell
New
[3/4] target-sparc: Don't flush TLB in cpu_load function
- - - -
-
-
-
2015-08-10
Peter Maydell
New
[4/4] target-sparc: Convert to VMStateDescription
- - - -
-
-
-
2015-08-10
Peter Maydell
New
[1/3] hw/sd/pxa2xx_mmci: convert to SysBusDevice object
- - - -
-
-
-
2015-08-11
Peter Maydell
New
[2/3] hw/sd/pxa2xx_mmci: Convert to VMStateDescription
- - - -
-
-
-
2015-08-11
Peter Maydell
New
[3/3] hw/sd/pxa2xx_mmci: Add reset function
- - - -
-
-
-
2015-08-11
Peter Maydell
New
[PULL,00/27] target-arm queue
- - - -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,01/27] target-arm: Add CNTVOFF_EL2
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,02/27] target-arm: Add CNTHCTL_EL2
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,03/27] target-arm: Rename and move gt_cnt_reset
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,04/27] target-arm: Pass timeridx as argument to various timer functions
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,05/27] target-arm: Add the Hypervisor timer
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,06/27] hw/arm/virt: Replace magic IRQ constants with macros
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,07/27] hw/arm/virt: Connect the Hypervisor timer
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,08/27] i.MX: Split UART emulator in a header file and a source file
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,09/27] i.MX: Move serial initialization to init/realize of DeviceClass.
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,10/27] i.MX:Fix Coding style for UART emulator.
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,11/27] i.MX: Split AVIC emulator in a header file and a source file
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,12/27] i.MX: Fix Coding style for AVIC emulator.
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,13/27] i.MX: Split CCM emulator in a header file and a source file
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,14/27] i.MX: Fix Coding style for CCM emulator
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,15/27] i.MX: Split EPIT emulator in a header file and a source file
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,16/27] i.MX: Fix Coding style for EPIT emulator
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,17/27] i.MX: Split GPT emulator in a header file and a source file
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,18/27] i.MX: Fix Coding style for GPT emulator
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,19/27] Merge memory_region_init_reservation() into memory_region_init_io()
1 - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,20/27] hw/arm/gic: Kill code duplication
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,21/27] Introduce gic_class_name() instead of repeating condition
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,22/27] target-arm: Add debug check for mismatched cpreg resets
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,23/27] target-arm: Add the AArch64 view of the Secure physical timer
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,24/27] target-arm: Add AArch32 banked register access to secure physical timer
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,25/27] hw/arm/virt: Wire up secure timer interrupt
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,26/27] hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[PULL,27/27] i.MX: Fix UART driver to work with unitialized "chardev" device
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[1/9] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
- - - -
-
-
-
2015-08-13
Peter Maydell
New
[2/9] target-arm: Improve semihosting debug prints
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[3/9] gdbstub: Implement gdb_do_syscallv()
- - - -
-
-
-
2015-08-13
Peter Maydell
New
[4/9] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[5/9] include/exec/softmmu-semi.h: Add support for 64-bit values
- - - -
-
-
-
2015-08-13
Peter Maydell
New
[6/9] target-arm/arm-semi.c: Support widening APIs to 64 bits
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[7/9] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[8/9] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
- - - -
-
-
-
2015-08-13
Peter Maydell
New
[9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
- - 1 -
-
-
-
2015-08-13
Peter Maydell
New
[v2,1/6] cputlb: Add functions for flushing TLB for a single MMU index
- - 1 -
-
-
-
2015-08-14
Peter Maydell
New
[v2,2/6] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
- - 1 -
-
-
-
2015-08-14
Peter Maydell
New
[v2,3/6] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
- - 1 -
-
-
-
2015-08-14
Peter Maydell
New
[v2,4/6] target-arm: Implement missing EL2 TLBI operations
- - 1 -
-
-
-
2015-08-14
Peter Maydell
New
[v2,5/6] target-arm: Implement missing EL3 TLB invalidate operations
- - 1 -
-
-
-
2015-08-14
Peter Maydell
New
[v2,6/6] target-arm: Implement AArch64 TLBI operations on IPAs
- - 1 -
-
-
-
2015-08-14
Peter Maydell
New
configure: Don't permit SDL or GTK on OSX
- - 2 -
-
-
-
2015-08-14
Peter Maydell
New
[v2,1/4] scripts/qemu-gdb: Split MtreeCommand into its own module
- - 1 -
-
-
-
2015-08-14
Peter Maydell
New
[v2,2/4] scripts/qemu-gdb: Split CoroutineCommand into its own file
- - 1 -
-
-
-
2015-08-14
Peter Maydell
New
[v2,3/4] scripts/qemu-gdb: Silently pass through SIGUSR1
- - - -
-
-
-
2015-08-14
Peter Maydell
New
[v2,4/4] scripts/qemu-gdb: Add brief comment describing usage
- - - -
-
-
-
2015-08-14
Peter Maydell
New
[PULL,00/20] target-arm queue
- - - -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,01/20] xlnx-zynqmp: Connect the four OCM banks
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,02/20] MAINTAINERS: Update Xilinx Maintainership
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,03/20] MAINTAINERS: Add ZynqMP to MAINTAINERS file
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,04/20] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,05/20] target-arm: Implement missing AMAIR registers
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,06/20] target-arm: Implement missing AFSR registers
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,07/20] target-arm: Implement missing ACTLR registers
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,08/20] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,09/20] target-arm: Wire up AArch64 EL2 and EL3 address translation ops
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,10/20] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,11/20] target-arm: Enable the AArch32 ATS12NSO ops
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,12/20] target-arm: Implement AArch32 ATS1H* operations
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,13/20] smbios: add smbios 3.0 support
1 - 1 2
-
-
-
2015-08-25
Peter Maydell
New
[PULL,14/20] smbios: implement smbios support for mach-virt
1 - 2 2
-
-
-
2015-08-25
Peter Maydell
New
[PULL,15/20] cputlb: Add functions for flushing TLB for a single MMU index
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,16/20] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,17/20] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,18/20] target-arm: Implement missing EL2 TLBI operations
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,19/20] target-arm: Implement missing EL3 TLB invalidate operations
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,20/20] target-arm: Implement AArch64 TLBI operations on IPAs
- - 1 -
-
-
-
2015-08-25
Peter Maydell
New
[PULL,00/18] target-arm queue
- - - -
-
-
-
2015-08-25
Peter Maydell
New
[9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
- - - -
-
-
-
2015-08-27
Peter Maydell
New
[PULL,00/27] target-arm queue
- - - -
-
-
-
2015-09-04
Peter Maydell
New
[PULL,01/27] arm: Use g_new() & friends where that makes obvious sense
- - 1 -
-
-
-
2015-09-04
Peter Maydell
New
[PULL,02/27] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
- - - -
-
-
-
2015-09-04
Peter Maydell
New
[PULL,03/27] target-arm: Improve semihosting debug prints
- - 1 1
-
-
-
2015-09-04
Peter Maydell
New
[PULL,04/27] gdbstub: Implement gdb_do_syscallv()
- - - 1
-
-
-
2015-09-04
Peter Maydell
New
[PULL,05/27] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
- - 1 1
-
-
-
2015-09-04
Peter Maydell
New
[PULL,06/27] include/exec/softmmu-semi.h: Add support for 64-bit values
- - - 1
-
-
-
2015-09-04
Peter Maydell
New
[PULL,07/27] target-arm/arm-semi.c: Support widening APIs to 64 bits
- - 1 1
-
-
-
2015-09-04
Peter Maydell
New
[PULL,08/27] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
- - 1 1
-
-
-
2015-09-04
Peter Maydell
New
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