Show patches with: State = Action Required       |   426684 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v10,02/16] target/riscv: fix clzw implementation to operate on arg1 target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 3 - --- 2021-09-04 Philipp Tomsich New
[v10,03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - - --- 2021-09-04 Philipp Tomsich New
[v10,04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 3 - --- 2021-09-04 Philipp Tomsich New
[v10,05/16] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - 2 - --- 2021-09-04 Philipp Tomsich New
[v10,06/16] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - 2 - --- 2021-09-04 Philipp Tomsich New
[v10,07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - 2 - --- 2021-09-04 Philipp Tomsich New
[v10,08/16] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - 2 - --- 2021-09-04 Philipp Tomsich New
[v10,09/16] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 2 - --- 2021-09-04 Philipp Tomsich New
[v10,10/16] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - 2 - --- 2021-09-04 Philipp Tomsich New
[v10,11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 2 - --- 2021-09-04 Philipp Tomsich New
[v10,12/16] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 3 - --- 2021-09-04 Philipp Tomsich New
[v10,13/16] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 2 - --- 2021-09-04 Philipp Tomsich New
[v10,14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 2 - --- 2021-09-04 Philipp Tomsich New
[v10,15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 3 - --- 2021-09-04 Philipp Tomsich New
[v10,16/16] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - - --- 2021-09-04 Philipp Tomsich New
[v11,01/16] target/riscv: Introduce temporary in gen_add_uw() target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 3 - --- 2021-09-11 Philipp Tomsich New
[v11,02/16] target/riscv: fix clzw implementation to operate on arg1 target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 3 - --- 2021-09-11 Philipp Tomsich New
[v11,03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 1 - --- 2021-09-11 Philipp Tomsich New
[v11,04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 3 - --- 2021-09-11 Philipp Tomsich New
[v11,05/16] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - 2 - --- 2021-09-11 Philipp Tomsich New
[v11,06/16] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - 2 - --- 2021-09-11 Philipp Tomsich New
[v11,07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - 2 - --- 2021-09-11 Philipp Tomsich New
[v11,08/16] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - 2 - --- 2021-09-11 Philipp Tomsich New
[v11,09/16] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 2 - --- 2021-09-11 Philipp Tomsich New
[v11,10/16] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - 2 - --- 2021-09-11 Philipp Tomsich New
[v11,11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 2 - --- 2021-09-11 Philipp Tomsich New
[v11,12/16] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 3 - --- 2021-09-11 Philipp Tomsich New
[v11,13/16] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 2 - --- 2021-09-11 Philipp Tomsich New
[v11,14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 2 - --- 2021-09-11 Philipp Tomsich New
[v11,15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - 3 - --- 2021-09-11 Philipp Tomsich New
[v11,16/16] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - - --- 2021-09-11 Philipp Tomsich New
[1/2] tcg: add dup_const_tl wrapper [1/2] tcg: add dup_const_tl wrapper - - - - --- 2021-09-28 Philipp Tomsich New
[2/2] target/riscv: Use dup_const_tl in orc.b to legalise truncation of constant [1/2] tcg: add dup_const_tl wrapper - - 1 - --- 2021-09-28 Philipp Tomsich New
plugin: add qemu_plugin_insn_symbol to qemu-plugins.symbols plugin: add qemu_plugin_insn_symbol to qemu-plugins.symbols - - - - --- 2021-09-29 Philipp Tomsich New
[v2,1/2] tcg: add dup_const_tl wrapper [v2,1/2] tcg: add dup_const_tl wrapper - - 2 - --- 2021-10-03 Philipp Tomsich New
[v2,2/2] target/riscv: Use dup_const_tl in orc.b to legalise truncation of constant [v2,1/2] tcg: add dup_const_tl wrapper - - 3 - --- 2021-10-03 Philipp Tomsich New
target/riscv: Fix orc.b implementation target/riscv: Fix orc.b implementation - 1 1 1 --- 2021-10-13 Philipp Tomsich New
target/riscv: Fix position of 'experimental' comment target/riscv: Fix position of 'experimental' comment - - 3 - --- 2022-01-06 Philipp Tomsich New
[v1,1/2] decodetree: Add an optional predicate-function for decoding [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - - --- 2022-01-09 Philipp Tomsich New
[v1,2/2] target/riscv: Add XVentanaCondOps custom extension [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - - --- 2022-01-09 Philipp Tomsich New
net/dump.c: Suppress spurious compiler warning net/dump.c: Suppress spurious compiler warning - - 1 - --- 2022-01-09 Philipp Tomsich New
[v2,1/2] target/riscv: iterate over a table of decoders [v2,1/2] target/riscv: iterate over a table of decoders - - - - --- 2022-01-13 Philipp Tomsich New
[v2,2/2] target/riscv: Add XVentanaCondOps custom extension [v2,1/2] target/riscv: iterate over a table of decoders - - - - --- 2022-01-13 Philipp Tomsich New
[v3,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-28 Philipp Tomsich New
[v3,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-28 Philipp Tomsich New
[v3,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-28 Philipp Tomsich New
[v3,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-28 Philipp Tomsich New
[v3,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-28 Philipp Tomsich New
[v3,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-28 Philipp Tomsich New
[v3,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-28 Philipp Tomsich New
[v4,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-30 Philipp Tomsich New
[v4,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-30 Philipp Tomsich New
[v4,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - - --- 2022-01-30 Philipp Tomsich New
[v4,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - - --- 2022-01-30 Philipp Tomsich New
[v4,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - - --- 2022-01-30 Philipp Tomsich New
[v4,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-30 Philipp Tomsich New
[v4,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 1 - --- 2022-01-30 Philipp Tomsich New
[v5,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-01-31 Philipp Tomsich New
[v5,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-01-31 Philipp Tomsich New
[v5,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-01-31 Philipp Tomsich New
[v5,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-01-31 Philipp Tomsich New
[v5,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-01-31 Philipp Tomsich New
[v5,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-01-31 Philipp Tomsich New
[v5,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-01-31 Philipp Tomsich New
[v6,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-02-02 Philipp Tomsich New
[v6,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-02-02 Philipp Tomsich New
[v6,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-02-02 Philipp Tomsich New
[v6,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-02-02 Philipp Tomsich New
[v6,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-02-02 Philipp Tomsich New
[v6,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-02-02 Philipp Tomsich New
[v6,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - 2 - --- 2022-02-02 Philipp Tomsich New
target/riscv: fix inverted checks for ext_zb[abcs] target/riscv: fix inverted checks for ext_zb[abcs] - 1 1 - --- 2022-02-03 Philipp Tomsich New
[1/2] target/riscv: fence.i: update decode pattern [1/2] target/riscv: fence.i: update decode pattern - - - - --- 2022-08-12 Philipp Tomsich New
[2/2] target/riscv: fence: reconcile with specification [1/2] target/riscv: fence.i: update decode pattern - - - - --- 2022-08-12 Philipp Tomsich New
[v1] target/riscv: update disas.c for xnor/orn/andn and slli.uw [v1] target/riscv: update disas.c for xnor/orn/andn and slli.uw - - 1 - --- 2023-01-20 Philipp Tomsich New
[v1,1/2] target/riscv: add Zicond as an experimental extension [v1,1/2] target/riscv: add Zicond as an experimental extension - - - - --- 2023-01-20 Philipp Tomsich New
[v1,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions [v1,1/2] target/riscv: add Zicond as an experimental extension - - - - --- 2023-01-20 Philipp Tomsich New
[v2,1/2] target/riscv: add Zicond as an experimental extension [v2,1/2] target/riscv: add Zicond as an experimental extension - - - - --- 2023-01-21 Philipp Tomsich New
[v2,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions [v2,1/2] target/riscv: add Zicond as an experimental extension - - - - --- 2023-01-21 Philipp Tomsich New
[v3,1/2] target/riscv: add Zicond as an experimental extension [v3,1/2] target/riscv: add Zicond as an experimental extension - - - - --- 2023-02-07 Philipp Tomsich New
[v3,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions [v3,1/2] target/riscv: add Zicond as an experimental extension - - - - --- 2023-02-07 Philipp Tomsich New
[v4,1/2] target/riscv: refactor Zicond support [v4,1/2] target/riscv: refactor Zicond support - - 1 - --- 2023-03-06 Philipp Tomsich New
[v4,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions [v4,1/2] target/riscv: refactor Zicond support - - 1 - --- 2023-03-06 Philipp Tomsich New
[v5,1/2] target/riscv: refactor Zicond support target/riscv: refactor Zicond and reuse in XVentanaCondOps 1 - 1 - --- 2023-03-07 Philipp Tomsich New
[v5,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions target/riscv: refactor Zicond and reuse in XVentanaCondOps 1 - 1 - --- 2023-03-07 Philipp Tomsich New
target-s390x: Mask the SIGP order_code to 8bit. - - 1 - --- 2015-08-18 Philipp Kern New
Fix DEBUG_* compilation of qcow2. - - - - --- 2011-08-04 Philipp Hahn New
Rate limit vnc_write_pixels_generic - - - - --- 2012-05-07 Philipp Hahn New
e1000: Don't set the Capabilities List bit - - - - --- 2012-10-19 Philipp Hahn New
1.1.1 -> 1.1.2 migrate /managedsave issue - - - - --- 2012-10-24 Philipp Hahn New
[BUG] qemu-1.1.2 [FIXED-BY] qcow2: Fix avail_sectors in cluster allocation code - - - - --- 2012-12-12 Philipp Hahn New
[BUG,RFC] block/vmdk.c: File name with space fails to open - - - - --- 2013-01-24 Philipp Hahn New
vmdk: Allow space in file name - - 1 - --- 2013-01-29 Philipp Hahn New
[for-1.4,0/2] fix migration failure from 1.3 due to SeaBIOS size change - - - - --- 2013-02-11 Philipp Hahn New
[BUG] 50MB/min logspam: dma: unregistered DMA channel used nchan=0 dma_pos=0 dma_len=1 - - - - --- 2014-05-09 Philipp Hahn New
hw/dma: Print error message only once - - - - --- 2014-09-09 Philipp Hahn New
[v2] hw/dma/i8257: Silence phony error message - - - - --- 2014-09-10 Philipp Hahn New
[v10] Support vhd type VHD_DIFFERENCING - - - - --- 2015-03-08 Philipp Hahn New
[libvirt,v2,3/8] Add support for fetching statistics of completed jobs - - - - --- 2016-05-09 Philipp Hahn New
[1/2] acpi_piix4: fix migration of gpe fields - - - - --- 2017-03-20 Philipp Hahn New
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