Patchwork QEMU Development

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Patch A/R/T Date Submitter Delegate State
[v2,27/35] target-arm: Implement AArch64 SCTLR_EL1 0 1 0 2014-01-31 Peter Maydell New
[v2,26/35] target-arm: Implement AArch64 memory attribute registers 0 1 0 2014-01-31 Peter Maydell New
[v2,25/35] target-arm: Implement AArch64 dummy MDSCR_EL1 0 1 0 2014-01-31 Peter Maydell New
[v2,24/35] target-arm: Implement AArch64 TLB invalidate ops 0 0 0 2014-01-31 Peter Maydell New
[v2,23/35] target-arm: Implement AArch64 cache invalidate/clean ops 0 1 0 2014-01-31 Peter Maydell New
[v2,22/35] target-arm: Implement AArch64 DAIF system register 0 1 0 2014-01-31 Peter Maydell New
[v2,21/35] target-arm: Implement AArch64 MIDR_EL1 0 1 0 2014-01-31 Peter Maydell New
[v2,20/35] target-arm: Implement AArch64 CurrentEL sysreg 0 1 0 2014-01-31 Peter Maydell New
[v2,19/35] target-arm: A64: Make cache ID registers visible to AArch64 0 1 0 2014-01-31 Peter Maydell New
[v2,18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg 0 1 0 2014-01-31 Peter Maydell New
[v2,17/35] target-arm: Remove failure status return from read/write_raw_cp_reg 0 1 0 2014-01-31 Peter Maydell New
[v2,16/35] target-arm: Remove unnecessary code now read/write fns can't fail 0 0 0 2014-01-31 Peter Maydell New
[v2,15/35] target-arm: Drop success/fail return from cpreg read and write functions 0 1 0 2014-01-31 Peter Maydell New
[v2,14/35] target-arm: Convert miscellaneous reginfo structs to accessfn 0 0 0 2014-01-31 Peter Maydell New
[v2,13/35] target-arm: Convert generic timer reginfo to accessfn 0 1 0 2014-01-31 Peter Maydell New
[v2,12/35] target-arm: Convert performance monitor reginfo to accesfn 0 1 0 2014-01-31 Peter Maydell New
[v2,11/35] target-arm: Split cpreg access checks out from read/write functions 0 1 0 2014-01-31 Peter Maydell New
[v2,10/35] target-arm: Stop underdecoding ARM946 PRBS registers 0 0 0 2014-01-31 Peter Maydell New
[v2,09/35] target-arm: A64: Implement MSR (immediate) instructions 0 0 0 2014-01-31 Peter Maydell New
[v2,08/35] target-arm: A64: Implement store-exclusive for system mode 0 0 0 2014-01-31 Peter Maydell New
[v2,07/35] target-arm: Add exception level to the AArch64 TB flags 0 0 0 2014-01-31 Peter Maydell New
[v2,06/35] target-arm: Log bad system register accesses with LOG_UNIMP 0 1 0 2014-01-31 Peter Maydell New
[v2,05/35] target-arm: Remove unused ARMCPUState sr substruct 0 1 0 2014-01-31 Peter Maydell New
[v2,04/35] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier 0 1 0 2014-01-31 Peter Maydell New
[v2,03/35] target-arm: Define names for SCTLR bits 0 0 0 2014-01-31 Peter Maydell New
[v2,02/35] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs 0 0 0 2014-01-31 Peter Maydell New
[v2,01/35] target-arm: Fix raw read and write functions on AArch64 registers 0 0 0 2014-01-31 Peter Maydell New
[PULL,v2,00/34] target-arm queue 0 0 0 2014-01-31 Peter Maydell New
[PULL,38/38] arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes 0 1 0 2014-01-29 Peter Maydell New
[PULL,37/38] arm_gic: Introduce define for GIC_NR_SGIS 0 1 0 2014-01-29 Peter Maydell New
[PULL,36/38] arm: vgic device control api support 0 0 0 2014-01-29 Peter Maydell New
[PULL,35/38] kvm: Common device control API functions 0 1 0 2014-01-29 Peter Maydell New
[PULL,34/38] kvm: Introduce kvm_arch_irqchip_create 0 1 0 2014-01-29 Peter Maydell New
[PULL,33/38] linux-headers: Update from Linus' master ba635f8 0 0 0 2014-01-29 Peter Maydell New
[PULL,32/38] target-arm: A64: Add SIMD shift by immediate 0 1 0 2014-01-29 Peter Maydell New
[PULL,31/38] target-arm: A64: Add simple SIMD 3-same floating point ops 0 1 0 2014-01-29 Peter Maydell New
[PULL,30/38] target-arm: A64: Add integer ops from SIMD 3-same group 0 1 0 2014-01-29 Peter Maydell New
[PULL,29/38] target-arm: A64: Add logic ops from SIMD 3 same group 0 1 0 2014-01-29 Peter Maydell New
[PULL,28/38] target-arm: A64: Add top level decode for SIMD 3-same group 0 1 0 2014-01-29 Peter Maydell New
[PULL,27/38] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops 0 1 0 2014-01-29 Peter Maydell New
[PULL,26/38] target-arm: A64: Add SIMD three-different ABDL instructions 0 1 0 2014-01-29 Peter Maydell New
[PULL,25/38] target-arm: A64: Add SIMD three-different multiply accumulate insns 0 1 0 2014-01-29 Peter Maydell New
[PULL,24/38] target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM 0 0 0 2014-01-29 Peter Maydell New
[PULL,23/38] target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM 0 0 0 2014-01-29 Peter Maydell New
[PULL,22/38] target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ 0 0 0 2014-01-29 Peter Maydell New
[PULL,21/38] target-arm: Add set_neon_rmode helper 0 1 0 2014-01-29 Peter Maydell New
[PULL,20/38] target-arm: Add support for AArch32 SIMD VRINTX 0 1 0 2014-01-29 Peter Maydell New
[PULL,19/38] target-arm: Add support for AArch32 FP VRINTX 0 0 0 2014-01-29 Peter Maydell New
[PULL,18/38] target-arm: Add support for AArch32 FP VRINTZ 0 0 0 2014-01-29 Peter Maydell New
[PULL,17/38] target-arm: Add support for AArch32 FP VRINTR 0 0 0 2014-01-29 Peter Maydell New
[PULL,16/38] target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM 0 0 0 2014-01-29 Peter Maydell New
[PULL,15/38] target-arm: Move arm_rmode_to_sf to a shared location. 0 1 0 2014-01-29 Peter Maydell New
[PULL,14/38] display: avoid multi-statement macro 0 0 0 2014-01-29 Peter Maydell New
[PULL,13/38] ZYNQ: Implement board MIDR control for Zynq 0 0 0 2014-01-29 Peter Maydell New
[PULL,12/38] ARM: Convert MIDR to a property 0 1 0 2014-01-29 Peter Maydell New
[PULL,11/38] hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting 0 1 0 2014-01-29 Peter Maydell New
[PULL,10/38] target-arm: A64: Add SIMD scalar copy instructions 0 1 0 2014-01-29 Peter Maydell New
[PULL,09/38] target-arm: A64: Add SIMD modified immediate group 0 1 0 2014-01-29 Peter Maydell New
[PULL,08/38] target-arm: A64: Add SIMD copy operations 0 1 0 2014-01-29 Peter Maydell New
[PULL,07/38] target-arm: A64: Add SIMD across-lanes instructions 0 1 0 2014-01-29 Peter Maydell New
[PULL,06/38] target-arm: A64: Add SIMD ZIP/UZP/TRN 0 1 0 2014-01-29 Peter Maydell New
[PULL,05/38] target-arm: A64: Add SIMD TBL/TBLX 0 1 0 2014-01-29 Peter Maydell New
[PULL,04/38] target-arm: A64: Add SIMD EXT 0 1 0 2014-01-29 Peter Maydell New
[PULL,03/38] target-arm: A64: Add decode skeleton for SIMD data processing insns 0 1 0 2014-01-29 Peter Maydell New
[PULL,02/38] target-arm: A64: Add SIMD ld/st single 0 1 0 2014-01-29 Peter Maydell New
[PULL,01/38] target-arm: A64: Add SIMD ld/st multiple 0 1 0 2014-01-29 Peter Maydell New
[PULL,00/38] target-arm queue 0 0 0 2014-01-29 Peter Maydell New
[21/21] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group 0 1 0 2014-01-26 Peter Maydell New
[20/21] target-arm: A64: Add 2-reg-misc REV* instructions 0 1 0 2014-01-26 Peter Maydell New
[19/21] target-arm: A64: Add narrowing 2-reg-misc instructions 0 1 0 2014-01-26 Peter Maydell New
[18/21] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT 0 1 0 2014-01-26 Peter Maydell New
[17/21] target-arm: A64: Implement 2-register misc compares, ABS, NEG 0 1 0 2014-01-26 Peter Maydell New
[16/21] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group 0 1 0 2014-01-26 Peter Maydell New
[15/21] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc 0 1 0 2014-01-26 Peter Maydell New
[14/21] target-arm: A64: Implement remaining integer scalar-3-same insns 0 1 0 2014-01-26 Peter Maydell New
[13/21] target-arm: A64: Implement scalar pairwise ops 0 1 0 2014-01-26 Peter Maydell New
[12/21] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR 0 1 0 2014-01-26 Peter Maydell New
[11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD 0 1 0 2014-01-26 Peter Maydell New
[10/21] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns 0 1 0 2014-01-26 Peter Maydell New
[09/21] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns 0 1 0 2014-01-26 Peter Maydell New
[08/21] target-arm: A64: Add SIMD shift by immediate 0 1 0 2014-01-26 Peter Maydell New
[07/21] target-arm: A64: Add simple SIMD 3-same floating point ops 0 1 0 2014-01-26 Peter Maydell New
[06/21] target-arm: A64: Add integer ops from SIMD 3-same group 0 1 0 2014-01-26 Peter Maydell New
[05/21] target-arm: A64: Add logic ops from SIMD 3 same group 0 1 0 2014-01-26 Peter Maydell New
[04/21] target-arm: A64: Add top level decode for SIMD 3-same group 0 1 0 2014-01-26 Peter Maydell New
[03/21] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops 0 1 0 2014-01-26 Peter Maydell New
[02/21] target-arm: A64: Add SIMD three-different ABDL instructions 0 1 0 2014-01-26 Peter Maydell New
[01/21] target-arm: A64: Add SIMD three-different multiply accumulate insns 0 1 0 2014-01-26 Peter Maydell New
[v2,7/8] target-arm: A64: Add simple SIMD 3-same floating point ops 0 0 0 2014-01-23 Peter Maydell New
tests/Makefile: Run qom-test for every architecture 0 1 0 2014-01-23 Peter Maydell New
[v2,8/8] target-arm: A64: Add SIMD shift by immediate 0 1 0 2014-01-23 Peter Maydell New
[v2,7/8] target-arm: A64: Add simple SIMD 3-same floating point ops 0 1 0 2014-01-23 Peter Maydell New
[v2,6/8] target-arm: A64: Add integer ops from SIMD 3-same group 0 1 0 2014-01-23 Peter Maydell New
[v2,5/8] target-arm: A64: Add logic ops from SIMD 3 same group 0 1 0 2014-01-23 Peter Maydell New
[v2,4/8] target-arm: A64: Add top level decode for SIMD 3-same group 0 1 0 2014-01-23 Peter Maydell New
[v2,3/8] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops 0 1 0 2014-01-23 Peter Maydell New
[v2,2/8] target-arm: A64: Add SIMD three-different ABDL instructions 0 1 0 2014-01-23 Peter Maydell New
[v2,1/8] target-arm: A64: Add SIMD three-different multiply accumulate insns 0 1 0 2014-01-23 Peter Maydell New
[v2,00/42] rework input handling, sdl2 support 0 0 0 2014-01-22 Peter Maydell New
[24/24] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI 0 0 0 2014-01-21 Peter Maydell New