Patchwork QEMU Development

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Patch A/R/T Date Submitter Delegate State
[v9,17/26] target-arm: make TTBCR banked 0 0 0 2014-11-05 Greg Bellows New
[v9,16/26] target-arm: make TTBR0/1 banked 0 0 0 2014-11-05 Greg Bellows New
[v9,15/26] target-arm: make CSSELR banked 0 1 0 2014-11-05 Greg Bellows New
[v9,14/26] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI 0 0 0 2014-11-05 Greg Bellows New
[v9,13/26] target-arm: add SCTLR_EL3 and make SCTLR banked 0 0 0 2014-11-05 Greg Bellows New
[v9,12/26] target-arm: add MVBAR support 0 1 0 2014-11-05 Greg Bellows New
[v9,11/26] target-arm: add SDER definition 0 1 0 2014-11-05 Greg Bellows New
[v9,10/26] target-arm: add NSACR register 0 1 0 2014-11-05 Greg Bellows New
[v9,09/26] target-arm: implement IRQ/FIQ routing to Monitor mode 0 1 0 2014-11-05 Greg Bellows New
[v9,08/26] target-arm: move AArch32 SCR into security reglist 0 1 0 2014-11-05 Greg Bellows New
[v9,07/26] target-arm: insert AArch32 cpregs twice into hashtable 0 0 0 2014-11-05 Greg Bellows New
[v9,06/26] target-arm: add secure state bit to CPREG hash 0 0 0 2014-11-05 Greg Bellows New
[v9,05/26] target-arm: add CPREG secure state support 0 1 0 2014-11-05 Greg Bellows New
[v9,04/26] target-arm: add non-secure Translation Block flag 0 1 0 2014-11-05 Greg Bellows New
[v9,03/26] target-arm: add banked register accessors 0 1 0 2014-11-05 Greg Bellows New
[v9,02/26] target-arm: add async excp target_el function 0 1 0 2014-11-05 Greg Bellows New
[v9,01/26] target-arm: extend async excp masking 0 0 0 2014-11-05 Greg Bellows New
State of ARM FIQ in Qemu 0 0 0 2014-11-03 Greg Bellows New
[v2,16/16] hw/intc/arm_gic: add gic_update() for grouping 0 0 0 2014-10-30 Greg Bellows New
[v2,15/16] hw/intc/arm_gic: Break out gic_update() function 0 0 0 2014-10-30 Greg Bellows New
[v2,14/16] hw/intc/arm_gic: Restrict priority view 0 0 0 2014-10-30 Greg Bellows New
[v2,13/16] hw/intc/arm_gic: Change behavior of IAR writes 0 0 0 2014-10-30 Greg Bellows New
[v2,12/16] hw/intc/arm_gic: Change behavior of EOIR writes 0 0 0 2014-10-30 Greg Bellows New
[v2,11/16] hw/intc/arm_gic: Handle grouping for GICC_HPPIR 0 0 0 2014-10-30 Greg Bellows New
[v2,10/16] hw/intc/arm_gic: Implement Non-secure view of RPR 0 0 0 2014-10-30 Greg Bellows New
[v2,09/16] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked 0 0 0 2014-10-30 Greg Bellows New
[v2,08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked 0 0 0 2014-10-30 Greg Bellows New
[v2,07/16] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked 0 0 0 2014-10-30 Greg Bellows New
[v2,06/16] hw/intc/arm_gic: Add Interrupt Group Registers 0 0 0 2014-10-30 Greg Bellows New
[v2,05/16] hw/intc/arm_gic: Add ns_access() function 0 0 0 2014-10-30 Greg Bellows New
[v2,04/16] hw/intc/arm_gic: Add Security Extensions property 0 0 0 2014-10-30 Greg Bellows New
[v2,03/16] hw/arm/virt.c: Wire FIQ between CPU <> GIC 0 0 0 2014-10-30 Greg Bellows New
[v2,02/16] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC 0 0 0 2014-10-30 Greg Bellows New
[v2,01/16] hw/intc/arm_gic: Request FIQ sources 0 0 0 2014-10-30 Greg Bellows New
[v8,27/27] target-arm: add cpu feature EL3 to CPUs with Security Extensions 0 0 0 2014-10-30 Greg Bellows New
[v8,26/27] target-arm: make MAIR0/1 banked 0 0 0 2014-10-30 Greg Bellows New
[v8,25/27] target-arm: make c13 cp regs banked (FCSEIDR, ...) 0 0 0 2014-10-30 Greg Bellows New
[v8,24/27] target-arm: make VBAR banked 0 1 0 2014-10-30 Greg Bellows New
[v8,23/27] target-arm: make PAR banked 0 0 0 2014-10-30 Greg Bellows New
[v8,22/27] target-arm: make IFAR/DFAR banked 0 0 0 2014-10-30 Greg Bellows New
[v8,21/27] target-arm: make DFSR banked 0 1 0 2014-10-30 Greg Bellows New
[v8,20/27] target-arm: make IFSR banked 0 0 0 2014-10-30 Greg Bellows New
[v8,19/27] target-arm: make DACR banked 0 0 0 2014-10-30 Greg Bellows New
[v8,18/27] target-arm: make c2_mask and c2_base_mask banked 0 0 0 2014-10-30 Greg Bellows New
[v8,17/27] target-arm: add TCR_EL3 and make TTBCR banked 0 0 0 2014-10-30 Greg Bellows New
[v8,16/27] target-arm: add TTBR0_EL3 and make TTBR0/1 banked 0 0 0 2014-10-30 Greg Bellows New
[v8,15/27] target-arm: make CSSELR banked 0 0 0 2014-10-30 Greg Bellows New
[v8,14/27] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI 0 0 0 2014-10-30 Greg Bellows New
[v8,13/27] target-arm: add SCTLR_EL3 and make SCTLR banked 0 0 0 2014-10-30 Greg Bellows New
[v8,12/27] target-arm: add MVBAR support 0 0 0 2014-10-30 Greg Bellows New
[v8,11/27] target-arm: add SDER definition 0 1 0 2014-10-30 Greg Bellows New
[v8,10/27] target-arm: add NSACR register 0 1 0 2014-10-30 Greg Bellows New
[v8,09/27] target-arm: implement IRQ/FIQ routing to Monitor mode 0 1 0 2014-10-30 Greg Bellows New
[v8,08/27] target-arm: move AArch32 SCR into security reglist 0 0 0 2014-10-30 Greg Bellows New
[v8,07/27] target-arm: insert AArch32 cpregs twice into hashtable 0 0 0 2014-10-30 Greg Bellows New
[v8,06/27] target-arm: add secure state bit to CPREG hash 0 0 0 2014-10-30 Greg Bellows New
[v8,05/27] target-arm: add CPREG secure state support 0 0 0 2014-10-30 Greg Bellows New
[v8,04/27] target-arm: add non-secure Translation Block flag 0 1 0 2014-10-30 Greg Bellows New
[v8,03/27] target-arm: add banked register accessors 0 1 0 2014-10-30 Greg Bellows New
[v8,02/27] target-arm: add async excp target_el function 0 0 0 2014-10-30 Greg Bellows New
[v8,01/27] target-arm: extend async excp masking 0 0 0 2014-10-30 Greg Bellows New
[v7,07/32] target-arm: extend async excp masking 0 0 0 2014-10-24 Greg Bellows New
[v7,32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions 0 0 0 2014-10-21 Greg Bellows New
[v7,31/32] target-arm: make MAIR0/1 banked 0 0 0 2014-10-21 Greg Bellows New
[v7,30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) 0 0 0 2014-10-21 Greg Bellows New
[v7,29/32] target-arm: make PAR banked 0 0 0 2014-10-21 Greg Bellows New
[v7,28/32] target-arm: make IFAR/DFAR banked 0 0 0 2014-10-21 Greg Bellows New
[v7,27/32] target-arm: make DFSR banked 0 0 0 2014-10-21 Greg Bellows New
[v7,26/32] target-arm: make IFSR banked 0 0 0 2014-10-21 Greg Bellows New
[v7,25/32] target-arm: make DACR banked 0 0 0 2014-10-21 Greg Bellows New
[v7,24/32] target-arm: make c2_mask and c2_base_mask banked 0 0 0 2014-10-21 Greg Bellows New
[v7,23/32] target-arm: add TCR_EL3 and make TTBCR banked 0 0 0 2014-10-21 Greg Bellows New
[v7,22/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked 0 0 0 2014-10-21 Greg Bellows New
[v7,21/32] target-arm: make CSSELR banked 0 0 0 2014-10-21 Greg Bellows New
[v7,20/32] target-arm: add SCTLR_EL3 and make SCTLR banked 0 0 0 2014-10-21 Greg Bellows New
[v7,19/32] target-arm: add MVBAR support 0 0 0 2014-10-21 Greg Bellows New
[v7,18/32] target-arm: add SDER definition 0 0 0 2014-10-21 Greg Bellows New
[v7,17/32] target-arm: add NSACR register 0 0 0 2014-10-21 Greg Bellows New
[v7,16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI 0 0 0 2014-10-21 Greg Bellows New
[v7,15/32] target-arm: implement IRQ/FIQ routing to Monitor mode 0 0 0 2014-10-21 Greg Bellows New
[v7,14/32] target-arm: move AArch32 SCR into security reglist 0 0 0 2014-10-21 Greg Bellows New
[v7,13/32] target-arm: insert AArch32 cpregs twice into hashtable 0 0 0 2014-10-21 Greg Bellows New
[v7,12/32] target-arm: add secure state bit to CPREG hash 0 0 0 2014-10-21 Greg Bellows New
[v7,11/32] target-arm: add CPREG secure state support 0 0 0 2014-10-21 Greg Bellows New
[v7,10/32] target-arm: add non-secure Translation Block flag 0 0 0 2014-10-21 Greg Bellows New
[v7,09/32] target-arm: add banked register accessors 0 0 0 2014-10-21 Greg Bellows New
[v7,08/32] target-arm: add async excp target_el function 0 0 0 2014-10-21 Greg Bellows New
[v7,07/32] target-arm: extend async excp masking 0 0 0 2014-10-21 Greg Bellows New
[v7,06/32] target-arm: A32: Emulate the SMC instruction 0 1 0 2014-10-21 Greg Bellows New
[v7,05/32] target-arm: make arm_current_el() return EL3 0 1 0 2014-10-21 Greg Bellows New
[v7,04/32] target-arm: rename arm_current_pl to arm_current_el 0 1 0 2014-10-21 Greg Bellows New
[v7,03/32] target-arm: reject switching to monitor mode 0 2 0 2014-10-21 Greg Bellows New
[v7,02/32] target-arm: add arm_is_secure() function 0 1 0 2014-10-21 Greg Bellows New
[v7,01/32] target-arm: increase arrays of registers R13 & R14 0 1 0 2014-10-21 Greg Bellows New
[v6,32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions 0 0 0 2014-10-10 Greg Bellows New
[v6,31/32] target-arm: make MAIR0/1 banked 0 0 0 2014-10-10 Greg Bellows New
[v6,30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) 0 0 0 2014-10-10 Greg Bellows New
[v6,29/32] target-arm: make PAR banked 0 0 0 2014-10-10 Greg Bellows New
[v6,28/32] target-arm: make IFAR/DFAR banked 0 0 0 2014-10-10 Greg Bellows New
[v6,27/32] target-arm: make DFSR banked 0 0 0 2014-10-10 Greg Bellows New