Show patches with: State = Action Required       |    Archived = No       |   202198 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,13/38] ZYNQ: Implement board MIDR control for Zynq - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,14/38] display: avoid multi-statement macro - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,15/38] target-arm: Move arm_rmode_to_sf to a shared location. - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,16/38] target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,17/38] target-arm: Add support for AArch32 FP VRINTR - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,18/38] target-arm: Add support for AArch32 FP VRINTZ - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,19/38] target-arm: Add support for AArch32 FP VRINTX - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,20/38] target-arm: Add support for AArch32 SIMD VRINTX - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,21/38] target-arm: Add set_neon_rmode helper - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,22/38] target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,23/38] target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,24/38] target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,25/38] target-arm: A64: Add SIMD three-different multiply accumulate insns - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,26/38] target-arm: A64: Add SIMD three-different ABDL instructions - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,27/38] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,28/38] target-arm: A64: Add top level decode for SIMD 3-same group - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,29/38] target-arm: A64: Add logic ops from SIMD 3 same group - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,30/38] target-arm: A64: Add integer ops from SIMD 3-same group - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,31/38] target-arm: A64: Add simple SIMD 3-same floating point ops - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,32/38] target-arm: A64: Add SIMD shift by immediate - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,33/38] linux-headers: Update from Linus' master ba635f8 - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,34/38] kvm: Introduce kvm_arch_irqchip_create - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,35/38] kvm: Common device control API functions - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,36/38] arm: vgic device control api support - - - - 0 0 0 2014-01-29 Peter Maydell New
[PULL,37/38] arm_gic: Introduce define for GIC_NR_SGIS - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,38/38] arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes - - 1 - 0 0 0 2014-01-29 Peter Maydell New
[PULL,v2,00/34] target-arm queue - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,01/35] target-arm: Fix raw read and write functions on AArch64 registers - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,02/35] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,03/35] target-arm: Define names for SCTLR bits - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,04/35] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,05/35] target-arm: Remove unused ARMCPUState sr substruct - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,06/35] target-arm: Log bad system register accesses with LOG_UNIMP - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,07/35] target-arm: Add exception level to the AArch64 TB flags - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,08/35] target-arm: A64: Implement store-exclusive for system mode - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,09/35] target-arm: A64: Implement MSR (immediate) instructions - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,10/35] target-arm: Stop underdecoding ARM946 PRBS registers - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,11/35] target-arm: Split cpreg access checks out from read/write functions - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,12/35] target-arm: Convert performance monitor reginfo to accesfn - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,13/35] target-arm: Convert generic timer reginfo to accessfn - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,14/35] target-arm: Convert miscellaneous reginfo structs to accessfn - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,15/35] target-arm: Drop success/fail return from cpreg read and write functions - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,16/35] target-arm: Remove unnecessary code now read/write fns can't fail - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,17/35] target-arm: Remove failure status return from read/write_raw_cp_reg - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,19/35] target-arm: A64: Make cache ID registers visible to AArch64 - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,20/35] target-arm: Implement AArch64 CurrentEL sysreg - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,21/35] target-arm: Implement AArch64 MIDR_EL1 - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,22/35] target-arm: Implement AArch64 DAIF system register - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,23/35] target-arm: Implement AArch64 cache invalidate/clean ops - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,24/35] target-arm: Implement AArch64 TLB invalidate ops - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,25/35] target-arm: Implement AArch64 dummy MDSCR_EL1 - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,26/35] target-arm: Implement AArch64 memory attribute registers - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,27/35] target-arm: Implement AArch64 SCTLR_EL1 - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,28/35] target-arm: Implement AArch64 TCR_EL1 - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,29/35] target-arm: Implement AArch64 VBAR_EL1 - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,30/35] target-arm: Implement AArch64 TTBR* - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,31/35] target-arm: Implement AArch64 MPIDR - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,32/35] target-arm: Implement AArch64 generic timers - - - - 0 0 0 2014-01-31 Peter Maydell New
[v2,33/35] target-arm: Implement AArch64 ID and feature registers - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,34/35] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,35/35] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI - - 1 - 0 0 0 2014-01-31 Peter Maydell New
[v2,01/13] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,02/13] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,03/13] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,04/13] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,05/13] target-arm: A64: Implement scalar pairwise ops - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,06/13] target-arm: A64: Implement remaining integer scalar-3-same insns - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,07/13] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,08/13] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,09/13] target-arm: A64: Implement 2-register misc compares, ABS, NEG - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,10/13] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,11/13] target-arm: A64: Add narrowing 2-reg-misc instructions - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,12/13] target-arm: A64: Add 2-reg-misc REV* instructions - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v2,13/13] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group - - 1 - 0 0 0 2014-02-01 Peter Maydell New
[v3,1/5] rules.mak: Support .cc as a C++ source file suffix - - 1 - 0 0 0 2014-02-05 Peter Maydell New
[v3,2/5] rules.mak: Link with C++ if we have a C++ compiler - - 1 - 0 0 0 2014-02-05 Peter Maydell New
[v3,3/5] disas: Add subset of libvixl sources for A64 disassembler - - 1 - 0 0 0 2014-02-05 Peter Maydell New
[v3,4/5] disas/libvixl: Fix upstream libvixl compilation issues - - 1 - 0 0 0 2014-02-05 Peter Maydell New
[v3,5/5] disas: Implement disassembly output for A64 - - - - 0 0 0 2014-02-05 Peter Maydell New
[1/8] target-arm: A64: Implement plain vector SIMD indexed element insns - - - - 0 0 0 2014-02-07 Peter Maydell New
[2/8] target-arm: A64: Implement long vector x indexed insns - - - - 0 0 0 2014-02-07 Peter Maydell New
[3/8] target-arm: A64: Implement SIMD scalar indexed instructions - - - - 0 0 0 2014-02-07 Peter Maydell New
[4/8] target-arm: A64: Implement scalar three different instructions - - - - 0 0 0 2014-02-07 Peter Maydell New
[5/8] target-arm: A64: Implement SIMD FP compare and set insns - - - - 0 0 0 2014-02-07 Peter Maydell New
[6/8] target-arm: A64: Implement floating point pairwise insns - - - - 0 0 0 2014-02-07 Peter Maydell New
[7/8] softfloat: Support halving the result of muladd operation - - - - 0 0 0 2014-02-07 Peter Maydell New
[8/8] target-arm: A64: Implement remaining 3-same instructions - - - - 0 0 0 2014-02-07 Peter Maydell New
[PULL,00/29] target-arm queue - - - - 0 0 0 2014-02-08 Peter Maydell New
[PULL,01/29] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns - - 1 - 0 0 0 2014-02-08 Peter Maydell New
[PULL,02/29] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns - - 1 - 0 0 0 2014-02-08 Peter Maydell New
[PULL,03/29] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD - - 1 - 0 0 0 2014-02-08 Peter Maydell New
[PULL,04/29] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR - - 1 - 0 0 0 2014-02-08 Peter Maydell New
[PULL,05/29] target-arm: A64: Implement scalar pairwise ops - - 1 - 0 0 0 2014-02-08 Peter Maydell New
[PULL,06/29] target-arm: A64: Implement remaining integer scalar-3-same insns - - 1 - 0 0 0 2014-02-08 Peter Maydell New
[PULL,07/29] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc - - 1 - 0 0 0 2014-02-08 Peter Maydell New
[PULL,08/29] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group - - 1 - 0 0 0 2014-02-08 Peter Maydell New
[PULL,09/29] target-arm: A64: Implement 2-register misc compares, ABS, NEG - - 1 - 0 0 0 2014-02-08 Peter Maydell New
[PULL,10/29] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT - - 1 - 0 0 0 2014-02-08 Peter Maydell New
[PULL,11/29] target-arm: A64: Add narrowing 2-reg-misc instructions - - 1 - 0 0 0 2014-02-08 Peter Maydell New
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