Patches

Show patches with: State = Action Required       |    Archived = No   
« 1 2 ... 505 506 5071485 1486 »
Patch A/R/T S/W/F Date Submitter Delegate State
[target-arm,v9,07/14] net: cadence_gem: Split state struct and type into header - 3 1 0 0 0 2015-05-15 Peter Crosthwaite New
[target-arm,v9,06/14] net: cadence_gem: Clean up variable names - 4 1 0 0 0 2015-05-15 Peter Crosthwaite New
[target-arm,v9,05/14] arm: xlnx-zynqmp: Connect CPU Timers to GIC - 1 1 0 0 0 2015-05-15 Peter Crosthwaite New
[target-arm,v9,04/14] arm: xlnx-zynqmp: Add GIC - - - 0 0 0 2015-05-15 Peter Crosthwaite New
[target-arm,v9,03/14] arm: Introduce Xilinx ZynqMP SoC - 2 1 0 0 0 2015-05-15 Peter Crosthwaite New
[target-arm,v9,02/14] target-arm: cpu64: Add support for Cortex-A53 1 1 - 0 0 0 2015-05-15 Peter Crosthwaite New
[target-arm,v9,01/14] target-arm: cpu64: generalise name of A57 regs - 2 - 0 0 0 2015-05-15 Peter Crosthwaite New
[target-arm,v8,14/14] arm: xlnx-ep108: Add bootloading - 1 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,13/14] arm: xlnx-ep108: Add external RAM - 1 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,12/14] arm: Add xlnx-ep108 machine - 3 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,11/14] arm: xlnx-zynqmp: Add UART support - 2 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,10/14] char: cadence_uart: Split state struct and type into header - 3 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,1/1] target-arm: Implements the ARM PMCCNTR register - - - 0 0 0 2014-02-21 Alistair Francis New
[target-arm,v8,09/14] char: cadence_uart: Clean up variable names - 3 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,08/14] arm: xlnx-zynqmp: Add GEM support - 1 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,07/14] net: cadence_gem: Split state struct and type into header - 3 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,06/14] net: cadence_gem: Clean up variable names - 4 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,05/14] arm: xlnx-zynqmp: Connect CPU Timers to GIC - 1 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,04/14] arm: xlnx-zynqmp: Add GIC - - - 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,03/14] arm: Introduce Xilinx ZynqMP SoC - 2 1 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,02/14] target-arm: cpu64: Add support for Cortex-A53 1 1 - 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v8,01/14] target-arm: cpu64: generalise name of A57 regs - 2 - 0 0 0 2015-05-08 Peter Crosthwaite New
[target-arm,v7,15/15] arm: xlnx-ep108: Add bootloading - 1 1 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,14/15] arm: xlnx-ep108: Add external RAM - 1 1 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,13/15] arm: Add xlnx-ep108 machine - 3 1 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,12/15] arm: xlnx-zynqmp: Add UART support - 2 1 0 0 0 2015-05-07 Peter Crosthwaite New
[target-arm,v7,11/15] char: cadence_uart: Split state struct and type into header - 3 1 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,10/15] char: cadence_uart: Clean up variable names - 3 1 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,1/1] target-arm: Implements the ARM PMCCNTR register - - - 0 0 0 2014-02-19 Alistair Francis New
[target-arm,v7,09/15] arm: xlnx-zynqmp: Add GEM support - 1 1 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,08/15] net: cadence_gem: Split state struct and type into header - 3 1 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,07/15] net: cadence_gem: Clean up variable names - 4 1 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,06/15] arm: xlnx-zynqmp: Connect CPU Timers to GIC - 1 1 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,05/15] arm: xlnx-zynqmp: Add GIC - - - 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,04/15] intc: arm_gic: Macroify the MemoryRegion size - - - 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,03/15] arm: Introduce Xilinx ZynqMP SoC - 2 1 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,02/15] target-arm: cpu64: Add support for cortex-a53 1 1 - 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v7,01/15] target-arm: cpu64: generalise name of A57 regs - 2 - 0 0 0 2015-05-06 Peter Crosthwaite New
[target-arm,v6,14/14] arm: xilinx-ep108: Add bootloading - 1 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v6,13/14] arm: xilinx-ep108: Add external RAM - 1 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v6,12/14] arm: Add xlnx-ep108 machine - 3 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v6,10/14] char: cadence_uart: Split state struct and type into header - 3 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v6,1/1] target-arm: Implements the ARM PMCCNTR register - - - 0 0 0 2014-02-17 Alistair Francis New
[target-arm,v6,09/14] char: cadence_uart: Clean up variable names - 3 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v6,07/14] net: cadence_gem: Split state struct and type into header - 3 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v6,06/14] net: cadence_gem: Clean up variable names - 4 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v6,05/14] arm: xlnx-zynqmp: Connect CPU Timers to GIC - 1 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v6,03/14] arm: Introduce Xilinx ZynqMP SoC - 2 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v6,02/14] target-arm: cpu64: Add support for cortex-a53 1 - - 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v6,01/14] target-arm: cpu64: generalise name of A57 regs - 1 - 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,5/5] arm: zynq: Connect CPU resets to SLCR - - - 0 0 0 2014-01-15 Peter Crosthwaite New
[target-arm,v5,4/5] arm: Implement reset GPIO. - - - 0 0 0 2014-01-15 Peter Crosthwaite New
[target-arm,v5,3/5] zynq_slcr: Implement CPU reset - 1 - 0 0 0 2014-01-15 Peter Crosthwaite New
[target-arm,v5,2/5] arm: zynq: added SMP support - 1 - 0 0 0 2014-01-15 Peter Crosthwaite New
[target-arm,v5,14/14] arm: xilinx-ep108: Add bootloading - 1 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,13/14] arm: xilinx-ep108: Add external RAM - 1 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,12/14] arm: Add xlnx-ep108 machine - 2 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,10/14] char: cadence_uart: Split state struct and type into header - 2 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,10/10] ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc - - - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v5,1/5] arm: zynq: Macroify OCM Base and Size - - - 0 0 0 2014-01-15 Peter Crosthwaite New
[target-arm,v5,1/1] target-arm: Implements the ARM PMCCNTR register - - - 0 0 0 2014-01-31 Alistair Francis New
[target-arm,v5,09/14] char: cadence_uart: Clean up variable names - 2 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,09/10] ARM: cpu: add "reset_hivecs" property - - - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v5,08/10] arm/highbank.c: Fix MPCore periphbase name - 1 - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v5,07/14] net: cadence_gem: Split state struct and type into header - 2 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,07/10] arm/xilinx_zynq: Implement CBAR initialisation - 1 - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v5,06/14] net: cadence_gem: Clean up variable names - 3 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,06/10] arm/xilinx_zynq: Use object_new() rather than cpu_arm_init() - 1 - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v5,05/14] arm: xlnx-zynqmp: Connect CPU Timers to GIC - - 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,05/10] arm/highbank: Fix CBAR initialisation - 1 - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v5,04/14] arm: xlnx-zynqmp: Add GIC - - - 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,04/10] arm/highbank: Use object_new() rather than cpu_arm_init() - 1 - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v5,03/14] arm: Introduce Xilinx ZynqMP SoC - 1 1 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,03/10] target-arm/cpu: Convert reset CBAR to a property - - - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v5,02/14] target-arm: cpu64: Add support for cortex-a53 - - - 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,02/10] target-arm: Define and use ARM_FEATURE_CBAR - 1 - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v5,01/14] target-arm: cpu64: generalise name of A57 regs - - - 0 0 0 2015-04-24 Peter Crosthwaite New
[target-arm,v5,01/10] target-arm/helper.c: Allow cp15.c15 dummy override - 1 - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v5,00/10] Fix Support for ARM CBAR and reset-hivecs - - - 0 0 0 2013-12-16 Peter Crosthwaite New
[target-arm,v4,7/7] target-arm: Implement pmccfiltr_write function - - - 0 0 0 2014-08-26 Peter Crosthwaite New
[target-arm,v4,6/7] target-arm: Remove old code and replace with new functions - - - 0 0 0 2014-08-26 Peter Crosthwaite New
[target-arm,v4,5/7] target-arm: Implement pmccntr_sync function - - - 0 0 0 2014-08-26 Peter Crosthwaite New
[target-arm,v4,4/7] target-arm: Add arm_ccnt_enabled function - - - 0 0 0 2014-08-26 Peter Crosthwaite New
[target-arm,v4,3/7] target-arm: Implement PMCCNTR_EL0 and related registers - - - 0 0 0 2014-08-26 Peter Crosthwaite New
[target-arm,v4,3/3] zynq_slcr: Implement CPU reset - - - 0 0 0 2014-01-02 Peter Crosthwaite New
[target-arm,v4,2/7] arm: Implement PMCCNTR 32b read-modify-write - 1 - 0 0 0 2014-08-26 Peter Crosthwaite New
[target-arm,v4,2/3] zynq_slcr: Add links to the CPUs - - - 0 0 0 2014-01-02 Peter Crosthwaite New
[target-arm,v4,16/16] arm: xlnx-zynqmp: Add PSCI setup - 1 - 0 0 0 2015-03-23 Peter Crosthwaite New
[target-arm,v4,15/16] arm: xilinx-ep108: Add bootloading - 1 - 0 0 0 2015-03-23 Peter Crosthwaite New
[target-arm,v4,14/16] arm: xilinx-ep108: Add external RAM - 1 - 0 0 0 2015-03-23 Peter Crosthwaite New
[target-arm,v4,13/16] arm: Add xlnx-ep108 machine - 2 - 0 0 0 2015-03-23 Peter Crosthwaite New
[target-arm,v4,12/12] ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc - - - 0 0 0 2013-12-11 Peter Crosthwaite New
[target-arm,v4,11/16] char: cadence_uart: Split state struct and type into header - 2 - 0 0 0 2015-03-23 Peter Crosthwaite New
[target-arm,v4,11/12] ARM: cpu: add "reset_hivecs" property - - - 0 0 0 2013-12-11 Peter Crosthwaite New
[target-arm,v4,10/16] char: cadence_uart: Clean up variable names - 2 - 0 0 0 2015-03-23 Peter Crosthwaite New
[target-arm,v4,10/12] arm/highbank.c: Fix MPCore periphbase name - 1 - 0 0 0 2013-12-11 Peter Crosthwaite New
[target-arm,v4,1/7] target-arm: Make the ARM PMCCNTR register 64-bit - - - 0 0 0 2014-08-26 Peter Crosthwaite New
[target-arm,v4,1/3] xilinx_zynq: added SMP support: - - - 0 0 0 2014-01-02 Peter Crosthwaite New
[target-arm,v4,1/1] target-arm: Implements the ARM PMCCNTR register - - - 0 0 0 2014-01-28 Alistair Francis New
[target-arm,v4,09/12] arm/xilinx_zynq: Implement CBAR initialisation - 1 - 0 0 0 2013-12-11 Peter Crosthwaite New
« 1 2 ... 505 506 5071485 1486 »