Show patches with: State = Action Required       |    Archived = No       |   426448 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,26/26] hw/riscv: shakti_c: Mark as not user creatable [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 1 --- 2021-10-07 Alistair Francis New
[PULL,25/26] hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() 1 - - - --- 2021-10-07 Alistair Francis New
[PULL,24/26] hw/dma: sifive_pdma: Fix Control.claim bit detection [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - 1 1 - --- 2021-10-07 Alistair Francis New
[PULL,23/26] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 1 --- 2021-10-07 Alistair Francis New
[PULL,22/26] hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 1 --- 2021-10-07 Alistair Francis New
[PULL,21/26] hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 1 --- 2021-10-07 Alistair Francis New
[PULL,20/26] hw/char: sifive_uart: Register device in 'input' category [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 - --- 2021-10-07 Alistair Francis New
[PULL,19/26] hw/char: shakti_uart: Register device in 'input' category [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 - --- 2021-10-07 Alistair Francis New
[PULL,18/26] hw/char: ibex_uart: Register device in 'input' category [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 - --- 2021-10-07 Alistair Francis New
[PULL,17/26] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 3 1 --- 2021-10-07 Alistair Francis New
[PULL,16/26] disas/riscv: Add Zb[abcs] instructions [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() 1 - - - --- 2021-10-07 Alistair Francis New
[PULL,15/26] target/riscv: Remove RVB (replaced by Zb[abcs]) [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 3 - --- 2021-10-07 Alistair Francis New
[PULL,14/26] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 - --- 2021-10-07 Alistair Francis New
[PULL,13/26] target/riscv: Add rev8 instruction, removing grev/grevi [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 - --- 2021-10-07 Alistair Francis New
[PULL,12/26] target/riscv: Add a REQUIRE_32BIT macro [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 3 - --- 2021-10-07 Alistair Francis New
[PULL,11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 - --- 2021-10-07 Alistair Francis New
[PULL,10/26] target/riscv: Reassign instructions to the Zbb-extension [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() 1 - 2 - --- 2021-10-07 Alistair Francis New
[PULL,09/26] target/riscv: Add instructions of the Zbc-extension [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 2 - --- 2021-10-07 Alistair Francis New
[PULL,08/26] target/riscv: Reassign instructions to the Zbs-extension [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() 1 - 2 - --- 2021-10-07 Alistair Francis New
[PULL,07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() 1 - 2 - --- 2021-10-07 Alistair Francis New
[PULL,06/26] target/riscv: Remove the W-form instructions from Zbs [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() 1 - 2 - --- 2021-10-07 Alistair Francis New
[PULL,05/26] target/riscv: Reassign instructions to the Zba-extension [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() 1 - 2 - --- 2021-10-07 Alistair Francis New
[PULL,04/26] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 3 - --- 2021-10-07 Alistair Francis New
[PULL,03/26] target/riscv: clwz must ignore high bits (use shift-left & changed logic) [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - - 1 - --- 2021-10-07 Alistair Francis New
[PULL,02/26] target/riscv: fix clzw implementation to operate on arg1 [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - 1 3 - --- 2021-10-07 Alistair Francis New
[PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() [PULL,01/26] target/riscv: Introduce temporary in gen_add_uw() - 1 3 - --- 2021-10-07 Alistair Francis New
[PULL,00/26] riscv-to-apply queue - - - - --- 2021-10-07 Alistair Francis New
[v7,8/8] tests/data/acpi/virt: Update binary files for PPTT hw/arm/virt: Introduce cpu topology support - - - - --- 2021-10-07 wangyanan (Y) New
[v7,7/8] hw/arm/virt-acpi-build: Generate PPTT table hw/arm/virt: Introduce cpu topology support - - 1 - --- 2021-10-07 wangyanan (Y) New
[v7,6/8] tests/data/acpi/virt: Add empty binary files for PPTT hw/arm/virt: Introduce cpu topology support - - - - --- 2021-10-07 wangyanan (Y) New
[v7,5/8] hw/acpi/aml-build: Add PPTT table hw/arm/virt: Introduce cpu topology support - - 1 - --- 2021-10-07 wangyanan (Y) New
[v7,4/8] hw/acpi/aml-build: Add Processor hierarchy node structure hw/arm/virt: Introduce cpu topology support - - 2 - --- 2021-10-07 wangyanan (Y) New
[v7,3/8] hw/arm/virt: Add cpu-map to device tree hw/arm/virt: Introduce cpu topology support - - - - --- 2021-10-07 wangyanan (Y) New
[v7,2/8] device_tree: Add qemu_fdt_add_path hw/arm/virt: Introduce cpu topology support - - 2 - --- 2021-10-07 wangyanan (Y) New
[v7,1/8] hw/arm/virt: Only describe cpu topology since virt-6.2 hw/arm/virt: Introduce cpu topology support - - 1 - --- 2021-10-07 wangyanan (Y) New
[v2,27/27] target/riscv: support for 128-bit satp Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,26/27] target/riscv: adding 128-bit access functions for some csrs Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,25/27] target/riscv: actual functions to realize crs 128-bit insns Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,24/27] target/riscv: modification of the trans_csrxx for 128-bit support Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,23/27] target/riscv: helper functions to wrap calls to 128-bit csr insns Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,22/27] target/riscv: adding high part of some csrs Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,21/27] target/riscv: div and rem insns on 128-bit Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,20/27] target/riscv: addition of the 'd' insns for 128-bit mult/div/rem Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,19/27] target/riscv: support for 128-bit base multiplications insns Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,18/27] target/riscv: 128-bit double word integer shift instructions Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,17/27] target/riscv: 128-bit double word integer arithmetic instructions Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,16/27] target/riscv: support for 128-bit loads and store Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,15/27] target/riscv: 128-bit support for instructions using gen_shift Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,13/27] target/riscv: rename a few gen function helpers Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,12/27] target/riscv: moving some insns close to similar insns Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,10/27] target/riscv: adding accessors to the registers upper part Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,09/27] target/riscv: setup everything so that riscv128-softmmu compiles Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,08/27] target/riscv: refactoring calls to gen_shift Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,07/27] target/riscv: refactoring calls to gen_arith Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,06/27] target/riscv: separation of bitwise logic and aritmetic helpers Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,05/27] target/riscv: additional macros to check instruction support Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,04/27] target/riscv: array for the 64 upper bits of 128-bit registers Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,03/27] target/riscv: adding upper 64 bits for misa Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,02/27] Int128.h: addition of a few 128-bit operations Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
[v2,01/27] memory: add a few defines for octo (128-bit) values Adding partial support for 128-bit riscv target - - - - --- 2021-10-06 Frédéric Pétrot New
spapr/xive: Use xive_esb_rw() to trigger interrupts spapr/xive: Use xive_esb_rw() to trigger interrupts - - - - --- 2021-10-06 Cédric Le Goater New
hw/elf_ops.h: switch to ssize_t for elf loader return type hw/elf_ops.h: switch to ssize_t for elf loader return type - - 1 - --- 2021-10-06 Luc Michel New
target/sh4: Split user/system helpers target/sh4: Split user/system helpers - - - - --- 2021-10-06 Philippe Mathieu-Daudé New
[v4,41/41] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,40/41] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only linux-user: Streamline handling of SIGSEGV 1 - 1 - --- 2021-10-06 Richard Henderson New
[v4,39/41] target/sparc: Make sparc_cpu_tlb_fill sysemu only linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,38/41] target/sh4: Make sh4_cpu_tlb_fill sysemu only linux-user: Streamline handling of SIGSEGV - - - - --- 2021-10-06 Richard Henderson New
[v4,37/41] target/s390x: Implement s390_cpu_record_sigsegv linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,36/41] target/s390x: Use probe_access_flags in s390_probe_access linux-user: Streamline handling of SIGSEGV - - - - --- 2021-10-06 Richard Henderson New
[v4,35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only linux-user: Streamline handling of SIGSEGV - - 2 - --- 2021-10-06 Richard Henderson New
[v4,34/41] target/ppc: Implement ppc_cpu_record_sigsegv linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,33/41] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,32/41] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,31/41] target/nios2: Implement nios2_cpu_record_sigsegv linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,30/41] target/mips: Make mips_cpu_tlb_fill sysemu only linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,29/41] target/microblaze: Make mb_cpu_tlb_fill sysemu only linux-user: Streamline handling of SIGSEGV - - - - --- 2021-10-06 Richard Henderson New
[v4,28/41] target/m68k: Make m68k_cpu_tlb_fill sysemu only linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,27/41] target/i386: Implement x86_cpu_record_sigsegv linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,26/41] target/hppa: Make hppa_cpu_tlb_fill sysemu only linux-user: Streamline handling of SIGSEGV - - - - --- 2021-10-06 Richard Henderson New
[v4,25/41] target/hexagon: Remove hexagon_cpu_tlb_fill linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,24/41] target/cris: Make cris_cpu_tlb_fill sysemu only linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,23/41] target/arm: Implement arm_cpu_record_sigsegv linux-user: Streamline handling of SIGSEGV - - - - --- 2021-10-06 Richard Henderson New
[v4,22/41] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,21/41] target/alpha: Implement alpha_cpu_record_sigsegv linux-user: Streamline handling of SIGSEGV - - - - --- 2021-10-06 Richard Henderson New
[v4,20/41] linux-user: Add cpu_loop_exit_sigsegv linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,19/41] hw/core: Add TCGCPUOps.record_sigsegv linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,18/41] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,17/41] linux-user/host/riscv: Improve host_signal_write linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,16/41] target/arm: Fixup comment re handle_cpu_signal linux-user: Streamline handling of SIGSEGV - - - - --- 2021-10-06 Richard Henderson New
[v4,15/41] linux-user/host/riscv: Populate host_signal.h linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,14/41] linux-user/host/mips: Populate host_signal.h linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,13/41] linux-user/host/s390: Populate host_signal.h linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,12/41] linux-user/host/aarch64: Populate host_signal.h linux-user: Streamline handling of SIGSEGV - - - - --- 2021-10-06 Richard Henderson New
[v4,11/41] linux-user/host/arm: Populate host_signal.h linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,10/41] linux-user/host/sparc: Populate host_signal.h linux-user: Streamline handling of SIGSEGV - - - - --- 2021-10-06 Richard Henderson New
[v4,09/41] linux-user/host/alpha: Populate host_signal.h linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,08/41] linux-user/host/ppc: Populate host_signal.h linux-user: Streamline handling of SIGSEGV - - 1 - --- 2021-10-06 Richard Henderson New
[v4,07/41] linux-user/host/x86: Populate host_signal.h linux-user: Streamline handling of SIGSEGV - - - - --- 2021-10-06 Richard Henderson New
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