Show patches with: State = Action Required       |   427148 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v15,6/8,RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions RISC-V Pointer Masking implementation - - 2 - --- 2021-10-20 Alexey Baturo New
[PULL,v2,07/44] tests: acpi: add testcase for intel_iommu (DMAR table) [PULL,v2,01/44] tests: acpi: dump table with failed checksum - - 1 - --- 2021-10-20 Michael S. Tsirkin New
[v15,5/8,RISCV_PM] Print new PM CSRs in QEMU logs RISC-V Pointer Masking implementation - - 2 - --- 2021-10-20 Alexey Baturo New
[v15,4/8,RISCV_PM] Add J extension state description RISC-V Pointer Masking implementation - - 1 - --- 2021-10-20 Alexey Baturo New
[v15,3/8,RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode RISC-V Pointer Masking implementation - - 1 - --- 2021-10-20 Alexey Baturo New
[PULL,v2,06/44] tests: acpi: whitelist new expected table tests/data/acpi/q35/DMAR.dmar [PULL,v2,01/44] tests: acpi: dump table with failed checksum - - 1 - --- 2021-10-20 Michael S. Tsirkin New
[v15,2/8,RISCV_PM] Add CSR defines for RISC-V PM extension RISC-V Pointer Masking implementation - - 1 - --- 2021-10-20 Alexey Baturo New
[v15,1/8,RISCV_PM] Add J-extension into RISC-V RISC-V Pointer Masking implementation - - 3 - --- 2021-10-20 Alexey Baturo New
[PULL,v2,05/44] tests: acpi: update expected tables blobs [PULL,v2,01/44] tests: acpi: dump table with failed checksum - - 1 - --- 2021-10-20 Michael S. Tsirkin New
[PULL,v2,04/44] tests: acpi: q35: test for x2APIC entries in SRAT [PULL,v2,01/44] tests: acpi: dump table with failed checksum - - 1 - --- 2021-10-20 Michael S. Tsirkin New
[PULL,v2,03/44] tests: acpi: whitelist expected tables for acpi/q35/xapic testcase [PULL,v2,01/44] tests: acpi: dump table with failed checksum - - 1 - --- 2021-10-20 Michael S. Tsirkin New
[PULL,v2,02/44] tests: qtest: add qtest_has_accel() to check if tested binary supports accelerator [PULL,v2,01/44] tests: acpi: dump table with failed checksum - - 1 - --- 2021-10-20 Michael S. Tsirkin New
[PULL,v2,01/44] tests: acpi: dump table with failed checksum [PULL,v2,01/44] tests: acpi: dump table with failed checksum - - 1 - --- 2021-10-20 Michael S. Tsirkin New
[PULL,v2,00/44] pc,pci,virtio: features, fixes, tests - - - - --- 2021-10-20 Michael S. Tsirkin New
pci: fix PCI resource reserve capability on BE pci: fix PCI resource reserve capability on BE - 3 1 1 --- 2021-10-20 Michael S. Tsirkin New
[V5,10/10] vhost-vdpa: multiqueue support vhost-vDPA multiqueue - - - - --- 2021-10-20 Jason Wang New
[V5,09/10] virtio-net: vhost control virtqueue support vhost-vDPA multiqueue - - - - --- 2021-10-20 Jason Wang New
[V5,08/10] vhost: record the last virtqueue index for the virtio device vhost-vDPA multiqueue - - - - --- 2021-10-20 Jason Wang New
[V5,07/10] virtio-net: use "queue_pairs" instead of "queues" when possible vhost-vDPA multiqueue - - - - --- 2021-10-20 Jason Wang New
[V5,06/10] vhost-net: control virtqueue support vhost-vDPA multiqueue - - - - --- 2021-10-20 Jason Wang New
[V5,05/10] net: introduce control client vhost-vDPA multiqueue - - - - --- 2021-10-20 Jason Wang New
[V5,04/10] vhost-vdpa: let net_vhost_vdpa_init() returns NetClientState * vhost-vDPA multiqueue - - - - --- 2021-10-20 Jason Wang New
[V5,03/10] vhost-vdpa: prepare for the multiqueue support vhost-vDPA multiqueue - - - - --- 2021-10-20 Jason Wang New
[V5,02/10] vhost-vdpa: classify one time request vhost-vDPA multiqueue - - - - --- 2021-10-20 Jason Wang New
[V5,01/10] vhost-vdpa: open device fd in net_init_vhost_vdpa() vhost-vDPA multiqueue - - 1 - --- 2021-10-20 Jason Wang New
[v6,15/15] target/riscv: Compute mstatus.sd on demand target/riscv: Rationalize XLEN and operand length - - 1 - --- 2021-10-20 Richard Henderson New
[v6,14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump target/riscv: Rationalize XLEN and operand length - - 1 - --- 2021-10-20 Richard Henderson New
[v6,13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,12/15] target/riscv: Use gen_unary_per_ol for RVB target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,11/15] target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Rationalize XLEN and operand length 1 - 1 - --- 2021-10-20 Richard Henderson New
[v6,10/15] target/riscv: Use gen_arith_per_ol for RVM target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,09/15] target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,08/15] target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,07/15] target/riscv: Properly check SEW in amo_op target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,06/15] target/riscv: Use REQUIRE_64BIT in amo_check64 target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,05/15] target/riscv: Add MXL/SXL/UXL to TB_FLAGS target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,04/15] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,03/15] target/riscv: Split misa.mxl and misa.ext target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,02/15] target/riscv: Create RISCVMXL enumeration target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v6,01/15] target/riscv: Move cpu_get_tb_cpu_state out of line target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-20 Richard Henderson New
[v4,8/8] target/riscv: zfh: add Zfhmin cpu property [v4,1/8] target/riscv: zfh: half-precision load and store - - 1 - --- 2021-10-20 Frank Chang New
[v4,7/8] target/riscv: zfh: implement zfhmin extension [v4,1/8] target/riscv: zfh: half-precision load and store - - 2 - --- 2021-10-20 Frank Chang New
[v4,6/8] target/riscv: zfh: add Zfh cpu property [v4,1/8] target/riscv: zfh: half-precision load and store - - 1 - --- 2021-10-20 Frank Chang New
[v4,5/8] target/riscv: zfh: half-precision floating-point classify [v4,1/8] target/riscv: zfh: half-precision load and store - - 2 - --- 2021-10-20 Frank Chang New
[v4,4/8] target/riscv: zfh: half-precision floating-point compare [v4,1/8] target/riscv: zfh: half-precision load and store - - 2 - --- 2021-10-20 Frank Chang New
[v4,3/8] target/riscv: zfh: half-precision convert and move [v4,1/8] target/riscv: zfh: half-precision load and store 1 - 1 - --- 2021-10-20 Frank Chang New
[v4,2/8] target/riscv: zfh: half-precision computational [v4,1/8] target/riscv: zfh: half-precision load and store - - 2 - --- 2021-10-20 Frank Chang New
[v4,1/8] target/riscv: zfh: half-precision load and store [v4,1/8] target/riscv: zfh: half-precision load and store - - 1 - --- 2021-10-20 Frank Chang New
[v2,6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 3 - --- 2021-10-20 Bin Meng New
[v2,5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 3 - --- 2021-10-20 Bin Meng New
[v2,4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 3 - --- 2021-10-20 Bin Meng New
[v2,3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 3 - --- 2021-10-20 Bin Meng New
[v2,2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 3 - --- 2021-10-20 Bin Meng New
[v2,1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 2 - --- 2021-10-20 Bin Meng New
[2/2] hmp: Support fd-based KVM stats query Support fd-based KVM stats - - - - --- 2021-10-19 Mark Kanda New
[1/2] qmp: Support fd-based KVM stats query Support fd-based KVM stats - - - - --- 2021-10-19 Mark Kanda New
[v2] gdbstub: Switch to the thread receiving a signal [v2] gdbstub: Switch to the thread receiving a signal - - - - --- 2021-10-19 Pavel Labath New
[24/24] bsd-user: add arm target build bsd-user: arm (32-bit) support 1 - 1 - --- 2021-10-19 Warner Losh New
[23/24] bsd-user/arm/target_arch_signal.h: arm get_ucontext_sigreturn bsd-user: arm (32-bit) support - - 1 - --- 2021-10-19 Warner Losh New
[22/24] bsd-user/arm/target_arch_signal.h: arm set_mcontext bsd-user: arm (32-bit) support - - 1 - --- 2021-10-19 Warner Losh New
[21/24] bsd-user/arm/target_arch_signal.h: arm get_mcontext bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[20/24] bsd-user/arm/target_arch_signal.h: arm set_sigtramp_args bsd-user: arm (32-bit) support - - 1 - --- 2021-10-19 Warner Losh New
[19/24] bsd-user/arm/target_arch_signal.h: arm user context and trapframe for signals bsd-user: arm (32-bit) support - - 1 - --- 2021-10-19 Warner Losh New
[18/24] bsd-user/arm/target_arch_signal.h: arm machine context for signals bsd-user: arm (32-bit) support - - 1 - --- 2021-10-19 Warner Losh New
[17/24] bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[16/24] bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[15/24] bsd-user/arm/target_arch_elf.h: arm get hwcap bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[14/24] bsd-user/arm/target_arch_elf.h: arm defines for ELF bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[13/24] bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread bsd-user: arm (32-bit) support - - - - --- 2021-10-19 Warner Losh New
[12/24] bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[11/24] bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[10/24] bsd-user/arm/target_arch_reg.h: Implement core dump register copying bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[09/24] bsd-user/arm/target_arch_cpu.h: Implement system call dispatch bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[08/24] bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[07/24] bsd-user/arm/target_arch_cpu.h: Implment trivial EXCP exceptions bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[06/24] bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[05/24] bsd-user/arm/target_arch_cpu.h: Implement target_cpu_clone_regs bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[04/24] bsd-user/arm/target_arch_cpu.h: CPU Loop definitions bsd-user: arm (32-bit) support - - 1 - --- 2021-10-19 Warner Losh New
[03/24] bsd-user/arm/target_arch_cpu.c: Target specific TLS routines bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[02/24] bsd-user/arm/target_syscall.h: Add copyright and update name bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[01/24] bsd-user/arm/target_arch_sysarch.h: Use consistent include guards bsd-user: arm (32-bit) support - - 2 - --- 2021-10-19 Warner Losh New
[v5,4/4] qapi/monitor: only allow 'keep' SetPasswordAction for VNC and deprecate VNC-related HMP/QMP fixes - - - - --- 2021-10-19 Stefan Reiter New
[v5,3/4] qapi/monitor: allow VNC display id in set/expire_password VNC-related HMP/QMP fixes - - - - --- 2021-10-19 Stefan Reiter New
[v5,2/4] qapi/monitor: refactor set/expire_password with enums VNC-related HMP/QMP fixes - - - - --- 2021-10-19 Stefan Reiter New
[v5,1/4] monitor/hmp: add support for flag argument with value VNC-related HMP/QMP fixes - - 1 - --- 2021-10-19 Stefan Reiter New
[v5,16/16] target/riscv: Compute mstatus.sd on demand target/riscv: Rationalize XLEN and operand length - - 1 - --- 2021-10-19 Richard Henderson New
[v5,15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump target/riscv: Rationalize XLEN and operand length - - 1 - --- 2021-10-19 Richard Henderson New
[v5,14/16] target/riscv: Align gprs and fprs in cpu_dump target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,12/16] target/riscv: Use gen_unary_per_ol for RVB target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,11/16] target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Rationalize XLEN and operand length 1 - 1 - --- 2021-10-19 Richard Henderson New
[v5,10/16] target/riscv: Use gen_arith_per_ol for RVM target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,09/16] target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,08/16] target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,07/16] target/riscv: Properly check SEW in amo_op target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,06/16] target/riscv: Use REQUIRE_64BIT in amo_check64 target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,03/16] target/riscv: Split misa.mxl and misa.ext target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
[v5,02/16] target/riscv: Create RISCVMXL enumeration target/riscv: Rationalize XLEN and operand length - - 2 - --- 2021-10-19 Richard Henderson New
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