Show patches with: State = Action Required       |   426992 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v9,50/76] target/riscv: rvv-1.0: slide instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,49/76] target/riscv: rvv-1.0: mask-register logical instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,48/76] target/riscv: rvv-1.0: floating-point compare instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,47/76] target/riscv: rvv-1.0: integer comparison instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,46/76] target/riscv: rvv-1.0: single-width saturating add and subtract instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,45/76] target/riscv: rvv-1.0: widening integer multiply-add instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,44/76] target/riscv: rvv-1.0: narrowing integer right shift instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,43/76] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,42/76] target/riscv: rvv-1.0: single-width bit shift instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,41/76] target/riscv: rvv-1.0: single-width averaging add and subtract instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,40/76] target/riscv: rvv-1.0: integer extension instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,39/76] target/riscv: rvv-1.0: whole register move instructions support vector extension v1.0 1 - - - --- 2021-10-29 Frank Chang New
[v9,38/76] target/riscv: rvv-1.0: floating-point scalar move instructions support vector extension v1.0 1 - - - --- 2021-10-29 Frank Chang New
[v9,37/76] target/riscv: rvv-1.0: floating-point move instruction support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,36/76] target/riscv: rvv-1.0: integer scalar move instructions support vector extension v1.0 1 - 1 - --- 2021-10-29 Frank Chang New
[v9,35/76] target/riscv: rvv-1.0: register gather instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,34/76] target/riscv: rvv-1.0: allow load element with sign-extended support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,33/76] target/riscv: rvv-1.0: element index instruction support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,32/76] target/riscv: rvv-1.0: iota instruction support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,31/76] target/riscv: rvv-1.0: set-X-first mask bit instructions support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,30/76] target/riscv: rvv-1.0: find-first-set mask bit instruction support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,29/76] target/riscv: rvv-1.0: count population in mask instruction support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,28/76] target/riscv: rvv-1.0: floating-point classify instructions support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,27/76] target/riscv: rvv-1.0: floating-point square-root instruction support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,25/76] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,24/76] target/riscv: rvv-1.0: load/store whole register instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,23/76] target/riscv: rvv-1.0: fault-only-first unit stride load support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,21/76] target/riscv: rvv-1.0: index load and store instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,20/76] target/riscv: rvv-1.0: stride load and store instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,19/76] target/riscv: rvv-1.0: configure instructions support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,18/76] target/riscv: rvv-1.0: remove amo operations instructions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,17/76] target/riscv: rvv:1.0: add translation-time nan-box helper function support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,16/76] target/riscv: introduce more imm value modes in translator functions support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,15/76] target/riscv: rvv-1.0: update check functions support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,14/76] target/riscv: rvv-1.0: add VMA and VTA support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,13/76] target/riscv: rvv-1.0: add fractional LMUL support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,12/76] target/riscv: rvv-1.0: remove MLEN calculations support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,10/76] target/riscv: rvv-1.0: add vlenb register support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,09/76] target/riscv: rvv-1.0: add vcsr register support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,07/76] target/riscv: rvv-1.0: add translation-time vector context status support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,06/76] target/riscv: rvv-1.0: introduce writable misa.v field support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,05/76] target/riscv: rvv-1.0: add sstatus VS field support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty support vector extension v1.0 - - 1 - --- 2021-10-29 Frank Chang New
[v9,03/76] target/riscv: rvv-1.0: add mstatus VS field support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,02/76] target/riscv: Use FIELD_EX32() to extract wd field support vector extension v1.0 - - 2 - --- 2021-10-29 Frank Chang New
[v9,01/76] target/riscv: drop vector 0.7.1 and add 1.0 support support vector extension v1.0 - - 3 - --- 2021-10-29 Frank Chang New
meson.build: Allow to disable OSS again meson.build: Allow to disable OSS again - 1 - - --- 2021-10-29 Thomas Huth New
[PULL,v2,18/18] target/riscv: change the api for RVF/RVD fmin/fmax [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration 1 - - - --- 2021-10-29 Alistair Francis New
[PULL,v2,17/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 - --- 2021-10-29 Alistair Francis New
[PULL,v2,16/18] target/riscv: remove force HS exception [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 - --- 2021-10-29 Alistair Francis New
[PULL,v2,15/18] target/riscv: fix VS interrupts forwarding to HS [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 - --- 2021-10-29 Alistair Francis New
[PULL,v2,14/18] target/riscv: Allow experimental J-ext to be turned on [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 3 - --- 2021-10-29 Alistair Francis New
[PULL,v2,13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Maski… [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 2 - --- 2021-10-29 Alistair Francis New
[PULL,v2,12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 2 - --- 2021-10-29 Alistair Francis New
[PULL,v2,11/18] target/riscv: Print new PM CSRs in QEMU logs [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 - --- 2021-10-29 Alistair Francis New
[PULL,v2,10/18] target/riscv: Add J extension state description [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 - --- 2021-10-29 Alistair Francis New
[PULL,v2,09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 - --- 2021-10-29 Alistair Francis New
[PULL,v2,08/18] target/riscv: Add CSR defines for RISC-V PM extension [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 - --- 2021-10-29 Alistair Francis New
[PULL,v2,07/18] target/riscv: Add J-extension into RISC-V [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 3 - --- 2021-10-29 Alistair Francis New
[PULL,v2,06/18] hw/riscv: opentitan: Fixup the PLIC context addresses [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - 1 1 - --- 2021-10-29 Alistair Francis New
[PULL,v2,05/18] hw/riscv: virt: Use the PLIC config helper function [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 2 1 --- 2021-10-29 Alistair Francis New
[PULL,v2,04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 2 1 --- 2021-10-29 Alistair Francis New
[PULL,v2,03/18] hw/riscv: sifive_u: Use the PLIC config helper function [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 2 1 --- 2021-10-29 Alistair Francis New
[PULL,v2,02/18] hw/riscv: boot: Add a PLIC config string function [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 2 - --- 2021-10-29 Alistair Francis New
[PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration [PULL,v2,01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 2 - --- 2021-10-29 Alistair Francis New
[PULL,v2,00/18] riscv-to-apply queue - - - - --- 2021-10-29 Alistair Francis New
[PULL,v2,60/60] softmmu: fix for "after access" watchpoints [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 1 - --- 2021-10-29 Richard Henderson New
[PULL,v2,59/60] softmmu: remove useless condition in watchpoint check [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 1 - --- 2021-10-29 Richard Henderson New
[PULL,v2,58/60] softmmu: fix watchpoint processing in icount mode [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,57/60] tcg/optimize: Propagate sign info for shifting [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,56/60] tcg/optimize: Propagate sign info for bit counting [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,55/60] tcg/optimize: Propagate sign info for setcond [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,54/60] tcg/optimize: Propagate sign info for logical operations [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 3 - --- 2021-10-29 Richard Henderson New
[PULL,v2,53/60] tcg/optimize: Optimize sign extensions [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,52/60] tcg/optimize: Use fold_xx_to_i for rem [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 1 - --- 2021-10-29 Richard Henderson New
[PULL,v2,51/60] tcg/optimize: Use fold_xi_to_x for div [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,50/60] tcg/optimize: Use fold_xi_to_x for mul [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,49/60] tcg/optimize: Use fold_xx_to_i for orc [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 3 - --- 2021-10-29 Richard Henderson New
[PULL,v2,48/60] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,47/60] tcg: Extend call args using the correct opcodes [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - 1 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,46/60] tcg/optimize: Sink commutative operand swapping into fold functions [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 1 - --- 2021-10-29 Richard Henderson New
[PULL,v2,45/60] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 3 - --- 2021-10-29 Richard Henderson New
[PULL,v2,44/60] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,43/60] tcg/optimize: Split out fold_masks [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,42/60] tcg/optimize: Split out fold_ix_to_i [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,41/60] tcg/optimize: Split out fold_xi_to_x [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 1 - --- 2021-10-29 Richard Henderson New
[PULL,v2,40/60] tcg/optimize: Split out fold_sub_to_neg [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 1 - --- 2021-10-29 Richard Henderson New
[PULL,v2,39/60] tcg/optimize: Split out fold_to_not [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 1 - --- 2021-10-29 Richard Henderson New
[PULL,v2,38/60] tcg/optimize: Add type to OptContext [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 1 - --- 2021-10-29 Richard Henderson New
[PULL,v2,37/60] tcg/optimize: Split out fold_xi_to_i [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,36/60] tcg/optimize: Split out fold_xx_to_x [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,35/60] tcg/optimize: Split out fold_xx_to_i [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,34/60] tcg/optimize: Split out fold_mov [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,33/60] tcg/optimize: Split out fold_dup, fold_dup2 [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,32/60] tcg/optimize: Split out fold_bswap [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
[PULL,v2,31/60] tcg/optimize: Split out fold_count_zeros [PULL,v2,01/60] qemu/int128: Add int128_{not,xor} - - 2 - --- 2021-10-29 Richard Henderson New
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