From patchwork Wed Jul 26 15:43:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Christophe Dubois X-Patchwork-Id: 1813298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R9zST0hsHz1yYc for ; Thu, 27 Jul 2023 02:12:25 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qOghW-00068T-B5; Wed, 26 Jul 2023 11:45:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qOgfZ-0003Y5-Af; Wed, 26 Jul 2023 11:43:21 -0400 Received: from relay3-d.mail.gandi.net ([2001:4b98:dc4:8::223]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qOgfX-0006B0-Ek; Wed, 26 Jul 2023 11:43:21 -0400 Received: by mail.gandi.net (Postfix) with ESMTPA id 718CF60006; Wed, 26 Jul 2023 15:43:13 +0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Cc: Jean-Christophe Dubois , qemu-devel@nongnu.org Subject: [PATCH 0/3] Complete i.MX6UL and i.MX7 processor for bare metal application. Date: Wed, 26 Jul 2023 17:43:05 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-GND-Sasl: jcd@tribudubois.net Received-SPF: pass client-ip=2001:4b98:dc4:8::223; envelope-from=jcd@tribudubois.net; helo=relay3-d.mail.gandi.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds a few unimplemented TZ devices (TZASC and CSU) to i.MX6UL and i.MX7 processors to avoid bare metal application to experiment "bus error" when acccessing these devices. It also adds some internal memory segments (OCRAM) to the i.MX7 to allow bare metal application to use them. Last, it adds the SRC device to the i.MX7 processor to allow bare metal application to start the secondary Cortex-A7 core. Note: When running Linux inside Qemu, the secondary core is started by calling PSCI API and Qemu is emulating PSCI without needing access to the SRC device. This is why Linux is using the 2 cores in Qemu even if the SRC is not implemented. This is not the case when running bare metal application (like u-boot itself) that do not rely on the PSCI service being available. Jean-Christophe Dubois (3): Rework i.MX6UL device implementation/instantiation Rework i.MX7 device implementation/instantiation Add i.MX7 SRC device implementation hw/arm/fsl-imx6ul.c | 163 ++++++++++++----- hw/arm/fsl-imx7.c | 204 ++++++++++++++++----- hw/misc/imx7_src.c | 289 ++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/arm/fsl-imx6ul.h | 149 +++++++++++++-- include/hw/arm/fsl-imx7.h | 348 +++++++++++++++++++++++++++--------- include/hw/misc/imx7_src.h | 68 +++++++ 7 files changed, 1038 insertions(+), 184 deletions(-) create mode 100644 hw/misc/imx7_src.c create mode 100644 include/hw/misc/imx7_src.h