mbox series

[for,9.0,v15,00/10] target/riscv: vector fixes

Message ID 20240314175704.478276-1-dbarboza@ventanamicro.com
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Series target/riscv: vector fixes | expand

Message

Daniel Henrique Barboza March 14, 2024, 5:56 p.m. UTC 
Hi,

The series was renamed to reflect that at this point we're fixing more
things than just vstart management.

In this new version a couple fixes were added:

- patch 3 (new) fixes the memcpy endianess in 'vmvr_v', as suggested by
  Richard;

- patch 5 (new) fixes ldst_whole insns to now clear vstart in all cases.
  The fix was proposed by Max.

Another notable change was made in patch 6 (patch 4 from v14). We're not
doing early exits in helpers that are gated by vstart_eq_zero. This was
found to cause side-effects with insns that wants to send faults if vl =
0, and for the rest it becomes a moot check since vstart is granted to
be zero beforehand.

Series based on master.

Patches missing acks: 3, 4, 5

Changes from v14:
- patch 3 (new):
  - make 'vmvr_v' big endian compliant
- patch 5 (new):
  - make ldst_whole insns clear vstart in all code paths
- patch 6 (patch 4 from v14):
  - do not add early exits on helpers that are gated with vstart_eq_zero
- v14 link: https://lore.kernel.org/qemu-riscv/20240313220141.427730-1-dbarboza@ventanamicro.com/

Daniel Henrique Barboza (9):
  target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
  trans_rvv.c.inc: set vstart = 0 in int scalar move insns
  target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
  target/riscv: always clear vstart in whole vec move insns
  target/riscv: always clear vstart for ldst_whole insns
  target/riscv/vector_helpers: do early exit when vstart >= vl
  target/riscv: remove 'over' brconds from vector trans
  trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
  target/riscv/vector_helper.c: optimize loops in ldst helpers

Ivan Klokov (1):
  target/riscv: enable 'vstart_eq_zero' in the end of insns

 target/riscv/insn_trans/trans_rvbf16.c.inc |  18 +-
 target/riscv/insn_trans/trans_rvv.c.inc    | 244 ++++++---------------
 target/riscv/insn_trans/trans_rvvk.c.inc   |  30 +--
 target/riscv/translate.c                   |   6 +
 target/riscv/vcrypto_helper.c              |  32 +++
 target/riscv/vector_helper.c               |  93 +++++++-
 target/riscv/vector_internals.c            |   4 +
 target/riscv/vector_internals.h            |   9 +
 8 files changed, 220 insertions(+), 216 deletions(-)

Comments

Alistair Francis March 20, 2024, 4:55 a.m. UTC | #1 
On Fri, Mar 15, 2024 at 3:59 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> The series was renamed to reflect that at this point we're fixing more
> things than just vstart management.
>
> In this new version a couple fixes were added:
>
> - patch 3 (new) fixes the memcpy endianess in 'vmvr_v', as suggested by
>   Richard;
>
> - patch 5 (new) fixes ldst_whole insns to now clear vstart in all cases.
>   The fix was proposed by Max.
>
> Another notable change was made in patch 6 (patch 4 from v14). We're not
> doing early exits in helpers that are gated by vstart_eq_zero. This was
> found to cause side-effects with insns that wants to send faults if vl =
> 0, and for the rest it becomes a moot check since vstart is granted to
> be zero beforehand.
>
> Series based on master.
>
> Patches missing acks: 3, 4, 5
>
> Changes from v14:
> - patch 3 (new):
>   - make 'vmvr_v' big endian compliant
> - patch 5 (new):
>   - make ldst_whole insns clear vstart in all code paths
> - patch 6 (patch 4 from v14):
>   - do not add early exits on helpers that are gated with vstart_eq_zero
> - v14 link: https://lore.kernel.org/qemu-riscv/20240313220141.427730-1-dbarboza@ventanamicro.com/
>
> Daniel Henrique Barboza (9):
>   target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
>   trans_rvv.c.inc: set vstart = 0 in int scalar move insns
>   target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
>   target/riscv: always clear vstart in whole vec move insns
>   target/riscv: always clear vstart for ldst_whole insns
>   target/riscv/vector_helpers: do early exit when vstart >= vl
>   target/riscv: remove 'over' brconds from vector trans
>   trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
>   target/riscv/vector_helper.c: optimize loops in ldst helpers
>
> Ivan Klokov (1):
>   target/riscv: enable 'vstart_eq_zero' in the end of insns

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/insn_trans/trans_rvbf16.c.inc |  18 +-
>  target/riscv/insn_trans/trans_rvv.c.inc    | 244 ++++++---------------
>  target/riscv/insn_trans/trans_rvvk.c.inc   |  30 +--
>  target/riscv/translate.c                   |   6 +
>  target/riscv/vcrypto_helper.c              |  32 +++
>  target/riscv/vector_helper.c               |  93 +++++++-
>  target/riscv/vector_internals.c            |   4 +
>  target/riscv/vector_internals.h            |   9 +
>  8 files changed, 220 insertions(+), 216 deletions(-)
>
> --
> 2.44.0
>
>