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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 00/61] target/hppa: Implement hppa64-cpu Date: Wed, 18 Oct 2023 14:50:34 -0700 Message-Id: <20231018215135.1561375-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This is the pa2.0 cpu that should populate Helge's C3700 workstation. I have adjusted both user and system binaries to always support the 64-bit cpu but default to the 32-bit cpu. I have not yet copied the linux kernel sigframe hackery to save the upper halves of the registers across signals. I couldn't get hppa-linux-gcc to produce 64-bit code with -march=2.0. I did some some manual testing with hppa64-linux-gnu, but that expects lp64 and a full 64-bit system library, so the tests has to be small and self-contained and also required some manual adjustment for the .got pointer references. But! With said adjustments we can run tests/tcg/multilib/sha512, which uses uint64_t a fair bit. Bugs were found and fixed. r~ Helge Deller (2): target/hppa: sar register allows only 5 bits on 32-bit CPU target/hppa: Fix interruption based on default PSW Richard Henderson (59): include/hw/elf: Remove truncating signed casts target/hppa: Remove get_temp target/hppa: Remove get_temp_tl target/hppa: Remove load_const target/hppa: Fix hppa64 case in machine.c target/hppa: Fix load in do_load_32 target/hppa: Truncate rotate count in trans_shrpw_sar target/hppa: Fix trans_ds for hppa64 target/hppa: Fix do_add, do_sub for hppa64 target/hppa: Fix bb_sar for hppa64 target/hppa: Fix extrw and depw with sar for hppa64 target/hppa: Introduce TYPE_HPPA64_CPU target/hppa: Make HPPA_BTLB_ENTRIES variable target/hppa: Implement cpu_list target/hppa: Implement hppa_cpu_class_by_name target/hppa: Update cpu_hppa_get/put_psw for hppa64 target/hppa: Handle absolute addresses for pa2.0 target/hppa: Adjust hppa_cpu_dump_state for hppa64 hw/hppa: Translate phys addresses for the cpu target/hppa: Fix hppa64 addressing target/hppa: Pass d to do_cond target/hppa: Pass d to do_sub_cond target/hppa: Pass d to do_log_cond target/hppa: Pass d to do_sed_cond target/hppa: Pass d to do_unit_cond linux-user/hppa: Fixes for TARGET_ABI32 target/hppa: Drop attempted gdbstub support for hppa64 target/hppa: Remove TARGET_HPPA64 target/hppa: Decode d for logical instructions target/hppa: Decode d for unit instructions target/hppa: Decode d for cmpclr instructions target/hppa: Decode d for add instructions target/hppa: Decode d for sub instructions target/hppa: Decode d for bb instructions target/hppa: Decode d for cmpb instructions target/hppa: Decode CMPIB double-word target/hppa: Decode ADDB double-word target/hppa: Implement LDD, LDCD, LDDA, STD, STDA target/hppa: Implement DEPD, DEPDI target/hppa: Implement EXTRD target/hppa: Implement SHRPD target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM target/hppa: Implement STDBY target/hppa: Implement IDTLBT, IITLBT target/hppa: Remove TARGET_REGISTER_BITS target/hppa: Remove most of the TARGET_REGISTER_BITS redirections target/hppa: Remove remaining TARGET_REGISTER_BITS redirections target/hppa: Use tcg_temp_new_i64 not tcg_temp_new target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 target/hppa: Implement HADD target/hppa: Implement HSUB target/hppa: Implement HAVG target/hppa: Implement HSHL, HSHR target/hppa: Implement HSHLADD, HSHRADD target/hppa: Implement MIXH, MIXW target/hppa: Implement PERMH target/hppa: Precompute zero into DisasContext target/hppa: Return zero for r0 from load_gpr target/hppa: Simplify trans_dep*_imm configs/targets/hppa-linux-user.mak | 1 + include/hw/elf_ops.h | 17 +- linux-user/hppa/target_elf.h | 2 +- target/hppa/cpu-param.h | 22 +- target/hppa/cpu-qom.h | 1 + target/hppa/cpu.h | 99 +- target/hppa/helper.h | 53 +- target/hppa/insns.decode | 169 ++- hw/hppa/machine.c | 93 +- linux-user/hppa/signal.c | 6 +- target/hppa/cpu.c | 52 +- target/hppa/gdbstub.c | 26 +- target/hppa/helper.c | 91 +- target/hppa/int_helper.c | 30 +- target/hppa/machine.c | 13 +- target/hppa/mem_helper.c | 141 +- target/hppa/op_helper.c | 310 +++- target/hppa/sys_helper.c | 13 +- target/hppa/translate.c | 2030 +++++++++++++++------------ 19 files changed, 1959 insertions(+), 1210 deletions(-)