| Message ID | 20231013212846.165724-1-richard.henderson@linaro.org |
|---|---|
| Headers | show |
| Series | target/sparc: Convert to decodetree | expand |
On 13/10/2023 22:27, Richard Henderson wrote: > While doing some other testing the other day, I noticed my sparc64 > chroot running particularly slowly. I think I know what the problem > is there, but fixing that was going to be particularly ugly with the > existing sparc translator. > > So I've converted the translator to something more managable. :-) > > I've only done avocado testing so far, fingers crossed. > > r~ Oh wow, that's amazing - looking into this has been on my TODO list for quite some time now :O FWIW I'm still struggling with hangs on sun4m which I've noticed a lot more whilst working on my ESP changes. I *think* it is the same issue I saw before when testing your original gen_helper_lookup_tb_ptr() conversion series for target/sparc, which did disappear in the final version of the series but I can now reproduce fairly consistently with git master. The reproducer here is easy with Solaris 8: ./build/qemu-system-sparc -cdrom sol8-cd1.iso -boot d Then when the splash screen appears keep wiggling the mouse until everything locks up. In my ESP traces I sometimes see random hangs where the trace-events would end with "esp_raise_irq()" and sit there for 10s of seconds before resuming, so both of this seems to suggest that interrupts aren't getting through when they should. Anyhow I can certainly give this series a spin on my OpenBIOS test images over the next few days as time allows. ATB, Mark. > Richard Henderson (85): > target/sparc: Set TCG_GUEST_DEFAULT_MO > configs: Enable MTTCG for sparc, sparc64 > target/sparc: Remove always-set cpu features > target/sparc: Add decodetree infrastructure > target/sparc: Define AM_CHECK for sparc32 > target/sparc: Move CALL to decodetree > target/sparc: Move BPcc and Bicc to decodetree > target/sparc: Move BPr to decodetree > target/sparc: Move FBPfcc and FBfcc to decodetree > target/sparc: Merge gen_cond with only caller > target/sparc: Merge gen_fcond with only caller > target/sparc: Merge gen_branch_[an] with only caller > target/sparc: Pass DisasCompare to advance_jump_cond > target/sparc: Move SETHI to decodetree > target/sparc: Move Tcc to decodetree > target/sparc: Move RDASR, STBAR, MEMBAR to decodetree > target/sparc: Move RDPSR, RDHPR to decodetree > target/sparc: Move RDWIM, RDPR to decodetree > target/sparc: Move RDTBR, FLUSHW to decodetree > target/sparc: Move WRASR to decodetree > target/sparc: Move WRPSR, SAVED, RESTORED to decodetree > target/sparc: Move WRWIM, WRPR to decodetree > target/sparc: Move WRTBR, WRHPR to decodetree > target/sparc: Move basic arithmetic to decodetree > target/sparc: Move ADDC to decodetree > target/sparc: Move MULX to decodetree > target/sparc: Move UMUL, SMUL to decodetree > target/sparc: Move SUBC to decodetree > target/sparc: Move UDIVX, SDIVX to decodetree > target/sparc: Move UDIV, SDIV to decodetree > target/sparc: Move TADD, TSUB, MULS to decodetree > target/sparc: Move SLL, SRL, SRA to decodetree > target/sparc: Move MOVcc, MOVR to decodetree > target/sparc: Move POPC to decodetree > target/sparc: Convert remaining v8 coproc insns to decodetree > target/sparc: Move JMPL, RETT, RETURN to decodetree > target/sparc: Move FLUSH, SAVE, RESTORE to decodetree > target/sparc: Move DONE, RETRY to decodetree > target/sparc: Split out resolve_asi > target/sparc: Drop ifdef around get_asi and friends > target/sparc: Split out ldst functions with asi pre-computed > target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX > target/sparc: Move simple integer load/store to decodetree > target/sparc: Move asi integer load/store to decodetree > target/sparc: Move LDSTUB, LDSTUBA to decodetree > target/sparc: Move SWAP, SWAPA to decodetree > target/sparc: Move CASA, CASXA to decodetree > target/sparc: Move PREFETCH, PREFETCHA to decodetree > target/sparc: Split out fp ldst functions with asi precomputed > target/sparc: Move simple fp load/store to decodetree > target/sparc: Move asi fp load/store to decodetree > target/sparc: Move LDFSR, STFSR to decodetree > target/sparc: Merge LDFSR, LDXFSR implementations > target/sparc: Move EDGE* to decodetree > target/sparc: Move ARRAY* to decodetree > target/sparc: Move ADDRALIGN* to decodetree > target/sparc: Move BMASK to decodetree > target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree > target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree > target/sparc: Use tcg_gen_vec_{add,sub}* > target/sparc: Move gen_ne_fop_FFF insns to decodetree > target/sparc: Move gen_ne_fop_DDD insns to decodetree > target/sparc: Move PDIST to decodetree > target/sparc: Move gen_gsr_fop_DDD insns to decodetree > target/sparc: Move gen_fop_FF insns to decodetree > target/sparc: Move gen_fop_DD insns to decodetree > target/sparc: Move FSQRTq to decodetree > target/sparc: Move gen_fop_FFF insns to decodetree > target/sparc: Move gen_fop_DDD insns to decodetree > target/sparc: Move gen_fop_QQQ insns to decodetree > target/sparc: Move FSMULD to decodetree > target/sparc: Move FDMULQ to decodetree > target/sparc: Move gen_fop_FD insns to decodetree > target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree > target/sparc: Move FqTOs, FqTOi to decodetree > target/sparc: Move FqTOd, FqTOx to decodetree > target/sparc: Move FiTOq, FsTOq to decodetree > target/sparc: Move FdTOq, FxTOq to decodetree > target/sparc: Move FMOVq, FNEGq, FABSq to decodetree > target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree > target/sparc: Convert FCMP, FCMPE to decodetree > target/sparc: Move FPCMP* to decodetree > target/sparc: Move FPACK16, FPACKFIX to decodetree > target/sparc: Convert FZERO, FONE to decodetree > target/sparc: Remove disas_sparc_legacy > > configs/targets/sparc-softmmu.mak | 1 + > configs/targets/sparc64-softmmu.mak | 1 + > linux-user/sparc/target_syscall.h | 6 +- > target/sparc/cpu.h | 73 +- > target/sparc/helper.h | 15 +- > target/sparc/insns.decode | 541 +++ > target/sparc/cpu.c | 8 +- > target/sparc/fop_helper.c | 17 +- > target/sparc/translate.c | 6692 +++++++++++++-------------- > target/sparc/vis_helper.c | 59 - > target/sparc/meson.build | 3 + > 11 files changed, 3804 insertions(+), 3612 deletions(-) > create mode 100644 target/sparc/insns.decode >
On 13/10/2023 22:27, Richard Henderson wrote: > While doing some other testing the other day, I noticed my sparc64 > chroot running particularly slowly. I think I know what the problem > is there, but fixing that was going to be particularly ugly with the > existing sparc translator. > > So I've converted the translator to something more managable. :-) > > I've only done avocado testing so far, fingers crossed. > > > r~ > > > Richard Henderson (85): > target/sparc: Set TCG_GUEST_DEFAULT_MO > configs: Enable MTTCG for sparc, sparc64 > target/sparc: Remove always-set cpu features > target/sparc: Add decodetree infrastructure > target/sparc: Define AM_CHECK for sparc32 > target/sparc: Move CALL to decodetree > target/sparc: Move BPcc and Bicc to decodetree > target/sparc: Move BPr to decodetree > target/sparc: Move FBPfcc and FBfcc to decodetree > target/sparc: Merge gen_cond with only caller > target/sparc: Merge gen_fcond with only caller > target/sparc: Merge gen_branch_[an] with only caller > target/sparc: Pass DisasCompare to advance_jump_cond > target/sparc: Move SETHI to decodetree > target/sparc: Move Tcc to decodetree > target/sparc: Move RDASR, STBAR, MEMBAR to decodetree > target/sparc: Move RDPSR, RDHPR to decodetree > target/sparc: Move RDWIM, RDPR to decodetree > target/sparc: Move RDTBR, FLUSHW to decodetree > target/sparc: Move WRASR to decodetree > target/sparc: Move WRPSR, SAVED, RESTORED to decodetree > target/sparc: Move WRWIM, WRPR to decodetree > target/sparc: Move WRTBR, WRHPR to decodetree > target/sparc: Move basic arithmetic to decodetree > target/sparc: Move ADDC to decodetree > target/sparc: Move MULX to decodetree > target/sparc: Move UMUL, SMUL to decodetree > target/sparc: Move SUBC to decodetree > target/sparc: Move UDIVX, SDIVX to decodetree > target/sparc: Move UDIV, SDIV to decodetree > target/sparc: Move TADD, TSUB, MULS to decodetree > target/sparc: Move SLL, SRL, SRA to decodetree > target/sparc: Move MOVcc, MOVR to decodetree > target/sparc: Move POPC to decodetree > target/sparc: Convert remaining v8 coproc insns to decodetree > target/sparc: Move JMPL, RETT, RETURN to decodetree > target/sparc: Move FLUSH, SAVE, RESTORE to decodetree > target/sparc: Move DONE, RETRY to decodetree > target/sparc: Split out resolve_asi > target/sparc: Drop ifdef around get_asi and friends > target/sparc: Split out ldst functions with asi pre-computed > target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX > target/sparc: Move simple integer load/store to decodetree > target/sparc: Move asi integer load/store to decodetree > target/sparc: Move LDSTUB, LDSTUBA to decodetree > target/sparc: Move SWAP, SWAPA to decodetree > target/sparc: Move CASA, CASXA to decodetree > target/sparc: Move PREFETCH, PREFETCHA to decodetree > target/sparc: Split out fp ldst functions with asi precomputed > target/sparc: Move simple fp load/store to decodetree > target/sparc: Move asi fp load/store to decodetree > target/sparc: Move LDFSR, STFSR to decodetree > target/sparc: Merge LDFSR, LDXFSR implementations > target/sparc: Move EDGE* to decodetree > target/sparc: Move ARRAY* to decodetree > target/sparc: Move ADDRALIGN* to decodetree > target/sparc: Move BMASK to decodetree > target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree > target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree > target/sparc: Use tcg_gen_vec_{add,sub}* > target/sparc: Move gen_ne_fop_FFF insns to decodetree > target/sparc: Move gen_ne_fop_DDD insns to decodetree > target/sparc: Move PDIST to decodetree > target/sparc: Move gen_gsr_fop_DDD insns to decodetree > target/sparc: Move gen_fop_FF insns to decodetree > target/sparc: Move gen_fop_DD insns to decodetree > target/sparc: Move FSQRTq to decodetree > target/sparc: Move gen_fop_FFF insns to decodetree > target/sparc: Move gen_fop_DDD insns to decodetree > target/sparc: Move gen_fop_QQQ insns to decodetree > target/sparc: Move FSMULD to decodetree > target/sparc: Move FDMULQ to decodetree > target/sparc: Move gen_fop_FD insns to decodetree > target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree > target/sparc: Move FqTOs, FqTOi to decodetree > target/sparc: Move FqTOd, FqTOx to decodetree > target/sparc: Move FiTOq, FsTOq to decodetree > target/sparc: Move FdTOq, FxTOq to decodetree > target/sparc: Move FMOVq, FNEGq, FABSq to decodetree > target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree > target/sparc: Convert FCMP, FCMPE to decodetree > target/sparc: Move FPCMP* to decodetree > target/sparc: Move FPACK16, FPACKFIX to decodetree > target/sparc: Convert FZERO, FONE to decodetree > target/sparc: Remove disas_sparc_legacy > > configs/targets/sparc-softmmu.mak | 1 + > configs/targets/sparc64-softmmu.mak | 1 + > linux-user/sparc/target_syscall.h | 6 +- > target/sparc/cpu.h | 73 +- > target/sparc/helper.h | 15 +- > target/sparc/insns.decode | 541 +++ > target/sparc/cpu.c | 8 +- > target/sparc/fop_helper.c | 17 +- > target/sparc/translate.c | 6692 +++++++++++++-------------- > target/sparc/vis_helper.c | 59 - > target/sparc/meson.build | 3 + > 11 files changed, 3804 insertions(+), 3612 deletions(-) > create mode 100644 target/sparc/insns.decode Hi Richard, I've had a chance to run this through the 32-bit set of my SPARC OpenBIOS tests and have found a few regressions summarised below by commit: 1 ./qemu-system-sparc -cdrom debian-40r4a-sparc-netinst.iso -boot d -bios ss5.bin (Boot with real SS-5 PROM instead of OpenBIOS) -> Hangs during PROM memory test -> Bisected to: 91b579b5293c4c5c3cfaf0214a5523b655dea4fe is the first bad commit commit 91b579b5293c4c5c3cfaf0214a5523b655dea4fe Author: Richard Henderson <richard.henderson@linaro.org> Date: Fri Oct 13 14:27:57 2023 -0700 target/sparc: Move JMPL, RETT, RETURN to decodetree Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013212846.165724-37-richard.henderson@linaro.org> 2. ./qemu-system-sparc -hda net702.qcow -snapshot (NetBSD 7) -> Hangs after displaying "Starting network" -> Bisected to: 736a90daf93404d7e9aabf3ea0056ba761385bb0 is the first bad commit commit 736a90daf93404d7e9aabf3ea0056ba761385bb0 Author: Richard Henderson <richard.henderson@linaro.org> Date: Fri Oct 13 14:27:46 2023 -0700 target/sparc: Move ADDC to decodetree Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013212846.165724-26-richard.henderson@linaro.org> 3. ./qemu-system-sparc -cdrom install52.iso -boot d (OpenBSD 5.2) -> Displays "sh: internal error" when selecting "(S)hell" option in the installer ./qemu-system-sparc -cdrom NetBSD-6.1.3-sparc.iso -boot d -> QEMU exits during early boot (Linux 3.8 test install) -> Linux panics during kernel boot -> Bisected to: 902ab5a4076f03be476c64c66b35ebc8a008c9c7 is the first bad commit commit 902ab5a4076f03be476c64c66b35ebc8a008c9c7 Author: Richard Henderson <richard.henderson@linaro.org> Date: Fri Oct 13 14:27:58 2023 -0700 target/sparc: Move FLUSH, SAVE, RESTORE to decodetree Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013212846.165724-38-richard.henderson@linaro.org> I hope this is enough to be going on with for now: once the 32-bit SPARC tests pass I can look at running through the longer set of 64-bit SPARC tests. ATB, Mark.
On 10/15/23 13:12, Mark Cave-Ayland wrote: > 1 ./qemu-system-sparc -cdrom debian-40r4a-sparc-netinst.iso -boot d -bios ss5.bin (Boot > with real SS-5 PROM instead of OpenBIOS) > > -> Hangs during PROM memory test > > -> Bisected to: > 91b579b5293c4c5c3cfaf0214a5523b655dea4fe is the first bad commit > commit 91b579b5293c4c5c3cfaf0214a5523b655dea4fe > Author: Richard Henderson <richard.henderson@linaro.org> > Date: Fri Oct 13 14:27:57 2023 -0700 > > target/sparc: Move JMPL, RETT, RETURN to decodetree > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > Message-Id: <20231013212846.165724-37-richard.henderson@linaro.org> Incorrectly translated "call %o7". Old decoder always computed the source into a temp; new decoder tries to use cpu_gpr[] directly. Clobbered %o7 with return address before setting npc. Fixed by moving the return address store later. r~
While doing some other testing the other day, I noticed my sparc64 chroot running particularly slowly. I think I know what the problem is there, but fixing that was going to be particularly ugly with the existing sparc translator. So I've converted the translator to something more managable. :-) I've only done avocado testing so far, fingers crossed. r~ Richard Henderson (85): target/sparc: Set TCG_GUEST_DEFAULT_MO configs: Enable MTTCG for sparc, sparc64 target/sparc: Remove always-set cpu features target/sparc: Add decodetree infrastructure target/sparc: Define AM_CHECK for sparc32 target/sparc: Move CALL to decodetree target/sparc: Move BPcc and Bicc to decodetree target/sparc: Move BPr to decodetree target/sparc: Move FBPfcc and FBfcc to decodetree target/sparc: Merge gen_cond with only caller target/sparc: Merge gen_fcond with only caller target/sparc: Merge gen_branch_[an] with only caller target/sparc: Pass DisasCompare to advance_jump_cond target/sparc: Move SETHI to decodetree target/sparc: Move Tcc to decodetree target/sparc: Move RDASR, STBAR, MEMBAR to decodetree target/sparc: Move RDPSR, RDHPR to decodetree target/sparc: Move RDWIM, RDPR to decodetree target/sparc: Move RDTBR, FLUSHW to decodetree target/sparc: Move WRASR to decodetree target/sparc: Move WRPSR, SAVED, RESTORED to decodetree target/sparc: Move WRWIM, WRPR to decodetree target/sparc: Move WRTBR, WRHPR to decodetree target/sparc: Move basic arithmetic to decodetree target/sparc: Move ADDC to decodetree target/sparc: Move MULX to decodetree target/sparc: Move UMUL, SMUL to decodetree target/sparc: Move SUBC to decodetree target/sparc: Move UDIVX, SDIVX to decodetree target/sparc: Move UDIV, SDIV to decodetree target/sparc: Move TADD, TSUB, MULS to decodetree target/sparc: Move SLL, SRL, SRA to decodetree target/sparc: Move MOVcc, MOVR to decodetree target/sparc: Move POPC to decodetree target/sparc: Convert remaining v8 coproc insns to decodetree target/sparc: Move JMPL, RETT, RETURN to decodetree target/sparc: Move FLUSH, SAVE, RESTORE to decodetree target/sparc: Move DONE, RETRY to decodetree target/sparc: Split out resolve_asi target/sparc: Drop ifdef around get_asi and friends target/sparc: Split out ldst functions with asi pre-computed target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX target/sparc: Move simple integer load/store to decodetree target/sparc: Move asi integer load/store to decodetree target/sparc: Move LDSTUB, LDSTUBA to decodetree target/sparc: Move SWAP, SWAPA to decodetree target/sparc: Move CASA, CASXA to decodetree target/sparc: Move PREFETCH, PREFETCHA to decodetree target/sparc: Split out fp ldst functions with asi precomputed target/sparc: Move simple fp load/store to decodetree target/sparc: Move asi fp load/store to decodetree target/sparc: Move LDFSR, STFSR to decodetree target/sparc: Merge LDFSR, LDXFSR implementations target/sparc: Move EDGE* to decodetree target/sparc: Move ARRAY* to decodetree target/sparc: Move ADDRALIGN* to decodetree target/sparc: Move BMASK to decodetree target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree target/sparc: Use tcg_gen_vec_{add,sub}* target/sparc: Move gen_ne_fop_FFF insns to decodetree target/sparc: Move gen_ne_fop_DDD insns to decodetree target/sparc: Move PDIST to decodetree target/sparc: Move gen_gsr_fop_DDD insns to decodetree target/sparc: Move gen_fop_FF insns to decodetree target/sparc: Move gen_fop_DD insns to decodetree target/sparc: Move FSQRTq to decodetree target/sparc: Move gen_fop_FFF insns to decodetree target/sparc: Move gen_fop_DDD insns to decodetree target/sparc: Move gen_fop_QQQ insns to decodetree target/sparc: Move FSMULD to decodetree target/sparc: Move FDMULQ to decodetree target/sparc: Move gen_fop_FD insns to decodetree target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree target/sparc: Move FqTOs, FqTOi to decodetree target/sparc: Move FqTOd, FqTOx to decodetree target/sparc: Move FiTOq, FsTOq to decodetree target/sparc: Move FdTOq, FxTOq to decodetree target/sparc: Move FMOVq, FNEGq, FABSq to decodetree target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree target/sparc: Convert FCMP, FCMPE to decodetree target/sparc: Move FPCMP* to decodetree target/sparc: Move FPACK16, FPACKFIX to decodetree target/sparc: Convert FZERO, FONE to decodetree target/sparc: Remove disas_sparc_legacy configs/targets/sparc-softmmu.mak | 1 + configs/targets/sparc64-softmmu.mak | 1 + linux-user/sparc/target_syscall.h | 6 +- target/sparc/cpu.h | 73 +- target/sparc/helper.h | 15 +- target/sparc/insns.decode | 541 +++ target/sparc/cpu.c | 8 +- target/sparc/fop_helper.c | 17 +- target/sparc/translate.c | 6692 +++++++++++++-------------- target/sparc/vis_helper.c | 59 - target/sparc/meson.build | 3 + 11 files changed, 3804 insertions(+), 3612 deletions(-) create mode 100644 target/sparc/insns.decode