mbox series

[00/20] riscv: split TCG/KVM accelerators from cpu.c

Message ID 20230825130853.511782-1-dbarboza@ventanamicro.com
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Series riscv: split TCG/KVM accelerators from cpu.c | expand

Message

Daniel Henrique Barboza Aug. 25, 2023, 1:08 p.m. UTC 
Based-on: 20230824221440.484675-1-dbarboza@ventanamicro.com
("[PATCH RESEND v8 00/20] riscv: 'max' CPU, detect user choice in TCG")

Hi,

The idea of this work was hinted at during a review [1] where Phil
mentioned that we should handle TCG specific constraints in
AccelCPUClass::cpu_realizefn(). While working on that I came across
the work done in x86 by Claudio Fontana in commit f5cc5a5c1 ("i386:
split cpu accelerators from cpu.c, using AccelCPUClass"). The design
implemented here is heavily inspired by Claudio's work.

An AccelCPUClass is an abstraction used by all QEMU accelerators that
are already streamlined in the init/realize process, doesn't matter if
we use it or not. Using accel classes allow us to split accel-specific
code from cpu.c into their own files, making easier to support
accel-specific builds in the future. It also gives us a template to
follow when adding new accelerators in the future.

The final goal, not entirely reached with this series, is to have cpu.c
hosting only common code for all accelerators, in particular the code
related to extensions support. We should declare extensions in cpu.c
then go to each accelerator class and do what you want with it. We're
not there yet due to how we rely on isa_edata_arr[] for both priv-spec
checks (a tcg only thing) and provide the riscv,isa string (all
accelerators). Trying to untangle priv-spec and isa_str is a fight for
another day.

You'll also notice that I didn't move all TCG related files to the 'tcg'
subdir. The reason is that Phil already did that here [2]:

"[PATCH 00/16] target/riscv: Allow building without TCG (KVM-only so far)"

and I deliberately avoided colliding with what he did. Phil's series focus
in splitting TCG includes and ifdefs in TCG specific files, while this
series focus in decoupling accel-speciic logic inside cpu.c.

The only behavior change implemented is in patch 20 where we block
vendor CPUs from using KVM. Most of the time I'm just juggling code
around to avoid breaking what we already have while trying to keep
patches review-sane.

No other behavior changes were intended with this series.

[1] https://lore.kernel.org/qemu-riscv/3b93823c-3d12-0d67-b814-54a3922d027f@linaro.org/
[2] https://lore.kernel.org/qemu-riscv/20230711121453.59138-1-philmd@linaro.org/


Daniel Henrique Barboza (20):
  target/riscv: introduce TCG AccelCPUClass
  target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
  target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
  target/riscv: move riscv_tcg_ops to tcg-cpu.c
  target/riscv/cpu.c: add 'user_extension_properties' class prop
  target/riscv: add 'max_features' CPU flag
  target/riscv/cpu.c: add .instance_post_init()
  target/riscv: move 'host' CPU declaration to kvm.c
  target/riscv/cpu.c: mark extensions arrays as 'const'
  target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
  target/riscv: introduce KVM AccelCPUClass
  target/riscv: move KVM only files to kvm subdir
  target/riscv/kvm: refactor kvm_riscv_init_user_properties()
  target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
  target/riscv/tcg: introduce tcg_cpu_instance_init()
  target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
  target/riscv/cpu.c: export isa_edata_arr[]
  target/riscv/cpu: move priv spec functions to tcg-cpu.c
  target/riscv: add 'tcg_supported' class property
  target/riscv: add 'kvm_supported' class property

 hw/riscv/virt.c                       |   2 +-
 target/riscv/cpu-qom.h                |   5 +
 target/riscv/cpu.c                    | 999 ++------------------------
 target/riscv/cpu.h                    |  31 +-
 target/riscv/cpu_cfg.h                |   1 +
 target/riscv/csr.c                    |   1 +
 target/riscv/{kvm.c => kvm/kvm-cpu.c} | 153 +++-
 target/riscv/{ => kvm}/kvm-stub.c     |   0
 target/riscv/{ => kvm}/kvm_riscv.h    |   1 -
 target/riscv/kvm/meson.build          |   2 +
 target/riscv/meson.build              |   4 +-
 target/riscv/tcg/meson.build          |   2 +
 target/riscv/tcg/tcg-cpu.c            | 864 ++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.h            |  28 +
 14 files changed, 1160 insertions(+), 933 deletions(-)
 rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (89%)
 rename target/riscv/{ => kvm}/kvm-stub.c (100%)
 rename target/riscv/{ => kvm}/kvm_riscv.h (95%)
 create mode 100644 target/riscv/kvm/meson.build
 create mode 100644 target/riscv/tcg/meson.build
 create mode 100644 target/riscv/tcg/tcg-cpu.c
 create mode 100644 target/riscv/tcg/tcg-cpu.h