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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lc1-20020a170906f90100b00988e953a586sm7869892ejb.61.2023.06.30.02.13.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 02:13:06 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Jeff Law , Tsukasa OI , liweiwei@iscas.ac.cn, Daniel Henrique Barboza , Liu Zhiwei , Rob Bradford Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH v4 0/3] riscv: Add support for the Zfa extension Date: Fri, 30 Jun 2023 11:13:00 +0200 Message-ID: <20230630091303.1676486-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Christoph Müllner This patch introduces the RISC-V Zfa extension. The Zfa specification can be found here: https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex The Zfa specifciation is frozen and is in public review since May 3, 2023: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg The first patch is mostly equal to v3 (plus resolved rebase issues and fixed whitespace issues). The second patch changes the implementation of fcvtmod.w.d to use float64_to_int64_modulo(), which is provided by a patchset from Richard Henderson: https://lists.nongnu.org/archive/html/qemu-devel/2023-05/msg07022.html The third test contains a test for fcvtmod.w.d, which was used for development. Since compiling this test requires Zfa support in the RISC-V toolchain (which is not given), this patch is not meant to be merged as of now. Changes in v4: * Rebase and resolve conflicts * Fix whitespace issue (thanks Rob) * Add patch to implemnt fcvtmod.w.d using float64_to_int64_modulo() * Add (demo) test for fcvtmod.w.d Changes in v3: * Add disassembler support * Enable Zfa by default * Remove forgotten comments in the decoder * Fix fli translation code (use movi instead of ld) * Tested against SPEC CPU2017 fprate * Use floatN_[min|max] for f[min|max]m.* instructions Changes in v2: * Remove calls to mark_fs_dirty() in comparison trans functions * Rewrite fround(nx) using float*_round_to_int() * Move fli* to translation unit and fix NaN-boxing of NaN values * Reimplement FCVTMOD.W.D * Add use of second register in trans_fmvp_d_x() Christoph Müllner (3): riscv: Add support for the Zfa extension target/riscv: Use float64_to_int64_modulo for fcvtmod.w.d DO NOT MERGE: tests/tcg/riscv64: Add test for fcvtmod.w.d disas/riscv.c | 151 ++++++ target/riscv/cpu.c | 8 + target/riscv/cpu_cfg.h | 1 + target/riscv/fpu_helper.c | 198 ++++++++ target/riscv/helper.h | 19 + target/riscv/insn32.decode | 26 ++ target/riscv/insn_trans/trans_rvzfa.c.inc | 529 ++++++++++++++++++++++ target/riscv/translate.c | 1 + tests/tcg/riscv64/Makefile.target | 6 + tests/tcg/riscv64/test-fcvtmod.c | 354 +++++++++++++++ 10 files changed, 1293 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzfa.c.inc create mode 100644 tests/tcg/riscv64/test-fcvtmod.c