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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id le8-20020a170907170800b0096f803afbe3sm7376156ejc.66.2023.05.30.06.18.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:18:45 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 0/9] disas/riscv: Add vendor extension support Date: Tue, 30 May 2023 15:18:34 +0200 Message-Id: <20230530131843.1186637-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=christoph.muellner@vrull.eu; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Christoph Müllner This series adds vendor extension support to the QEMU disassembler for RISC-V. The following vendor extensions are covered: * XThead{Ba,Bb,Bs,Cmo,CondMov,FMemIdx,Fmv,Mac,MemIdx,MemPair,Sync} * XVentanaCondOps So far, there have been two attempts to add vendor extension support to the QEMU disassembler. The first one [1] was posted in August 2022 by LIU Zhiwei and attempts to separate vendor extension specifics from standard extension code in combination with a patch that introduced support for XVentanaCondOps. The second one [2] was posted in March 2023 by me and added XThead* support without separating the vendor extensions from the standard code. This patchset represents the third attempt to add vendor extension support to the QEMU disassembler. It adds all features of the previous attempts and integrates them into a patchset that uses the same mechanism for testing the extension availability like translate.c (using the booleans RISCVCPUConfig::ext_*). To achieve that, a couple of patches were needed to restructure the existing code. Note, that this patchset allows an instruction encoder function for each vendor extension, but operand decoding and instruction printing remains common code. This is irrelevant for XVentanaCondOps, but the patch for the XThead* extensions includes changes in riscv.c and riscv.h. This could be changed to force more separation with the cost of duplication. The first patch of this series is cherry-picked from LIU Zhiwei's series. It was reviewed by Alistair Francis and Richard Henderson, but never made it on master. I've added "Reviewed-by" tags to the commit. I've added "Co-developed-by" tags to those commits that are derived from the series of LIU Zhiwei. [1] https://lists.nongnu.org/archive/html/qemu-devel/2022-08/msg03662.html [2] https://lists.nongnu.org/archive/html/qemu-devel/2023-03/msg04566.html Christoph Müllner (8): target/riscv: Factor out RISCVCPUConfig from cpu.h disas/riscv: Move types/constants to new header file disas/riscv: Make rv_op_illegal a shared enum value disas/riscv: Encapsulate opcode_data into decode target/riscv/cpu: Share RISCVCPUConfig with disassembler disas/riscv: Provide infrastructure for vendor extensions disas/riscv: Add support for XVentanaCondOps disas/riscv: Add support for XThead* instructions LIU Zhiwei (1): target/riscv: Use xl instead of mxl for disassemble disas/meson.build | 6 +- disas/riscv-xthead.c | 707 ++++++++++++++++++++++++++++++++++++++ disas/riscv-xthead.h | 28 ++ disas/riscv-xventana.c | 41 +++ disas/riscv-xventana.h | 18 + disas/riscv.c | 384 ++++++--------------- disas/riscv.h | 297 ++++++++++++++++ target/riscv/cpu-config.h | 159 +++++++++ target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 114 +----- target/riscv/translate.c | 27 +- 11 files changed, 1374 insertions(+), 413 deletions(-) create mode 100644 disas/riscv-xthead.c create mode 100644 disas/riscv-xthead.h create mode 100644 disas/riscv-xventana.c create mode 100644 disas/riscv-xventana.h create mode 100644 disas/riscv.h create mode 100644 target/riscv/cpu-config.h