From patchwork Fri Apr 28 14:47:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lawrence Hunter X-Patchwork-Id: 1775041 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q7Fsj2x0Gz23td for ; Sat, 29 Apr 2023 00:51:05 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOd-0006CA-3k; Fri, 28 Apr 2023 10:48:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOa-000658-7a; Fri, 28 Apr 2023 10:48:24 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOR-00027P-VZ; Fri, 28 Apr 2023 10:48:23 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOH-005zz5-IM; Fri, 28 Apr 2023 15:48:05 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, Lawrence Hunter Subject: [PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support Date: Fri, 28 Apr 2023 15:47:38 +0100 Message-Id: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patchset provides an implementation for Zvbb, Zvbc, Zvkned, Zvknh, Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography extensions as per the v20230425 version of the specification(1) (6a7ae7f2). This is an update to the patchset submitted to qemu-devel on Monday, 17 Apr 2023 14:58:36 +0100. v2: squashed commits into one commit per extension with separate commits for each refactoring unified trans_rvzvk*.c.inc files into one trans_rvvk.c.inc style fixes in insn32.decode and other files added macros for EGS values in translation functions. updated from v20230303 to v20230407 of the spec: Zvkb has been split into Zvbb and Zvbc vbrev, vclz, vctz, vcpop and vwsll have been added to Zvbb. v3: New patch 03/19 removes redundant “cpu_vl == 0” checks from trans_rvv.c.inc Introduction of new tcg ops has been factored out of patch 11/19 and into 09/19 These ops are now added to non riscv-specific files As v20230425 is a freeze candidate, we are not expecting any significant changes to the specification or this patch series. Please note that the Zvkt data-independent execution latency extension (and all extensions including it) has not been implemented, and we would recommend not using these patches in an environment where timing attacks are an issue. Work performed by Dickon, Lawrence, Nazar, Kiran, and William from Codethink sponsored by SiFive, as well as Max Chou and Frank Chang from SiFive. For convenience we have created a git repo with our patches on top of a recent master. https://github.com/CodethinkLabs/qemu-ct https://github.com/riscv/riscv-crypto/releases Thanks to those who have already reviewed: Richard Henderson richard.henderson@linaro.org [PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro [PATCH v2 04/17] target/riscv: Move vector translation checks [PATCH v2 05/17] target/riscv: Refactor translation of vector-widening instruction [PATCH v2 07/17] qemu/bitops.h: Limit rotate amounts [PATCH v2 08/17] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers [PATCH v2 14/17] crypto: Create sm4_subword Alistair Francis alistair.francis@wdc.com [PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro Philipp Tomsich philipp.tomsich@vrull.eu Various v1 reviews Christoph Müllner christoph.muellner@vrull.eu Various v1 reviews Dickon Hood (3): target/riscv: Refactor translation of vector-widening instruction qemu/bitops.h: Limit rotate amounts target/riscv: Add Zvbb ISA extension support Kiran Ostrolenk (5): target/riscv: Refactor some of the generic vector functionality target/riscv: Refactor vector-vector translation macro target/riscv: Refactor some of the generic vector functionality qemu/host-utils.h: Add clz and ctz functions for lower-bit integers target/riscv: Add Zvknh ISA extension support Lawrence Hunter (2): target/riscv: Add Zvbc ISA extension support target/riscv: Add Zvksh ISA extension support Max Chou (3): crypto: Create sm4_subword crypto: Add SM4 constant parameter CK target/riscv: Add Zvksed ISA extension support Nazar Kazakov (6): target/riscv: Remove redundant "cpu_vl == 0" checks target/riscv: Move vector translation checks tcg: Add andcs and rotrs tcg gvec ops target/riscv: Add Zvkned ISA extension support target/riscv: Add Zvkg ISA extension support target/riscv: Expose Zvk* and Zvb[b,c] cpu properties accel/tcg/tcg-runtime-gvec.c | 11 + accel/tcg/tcg-runtime.h | 1 + crypto/sm4.c | 10 + include/crypto/sm4.h | 9 + include/qemu/bitops.h | 24 +- include/qemu/host-utils.h | 54 ++ include/tcg/tcg-op-gvec.h | 4 + target/arm/tcg/crypto_helper.c | 10 +- target/riscv/cpu.c | 39 + target/riscv/cpu.h | 8 + target/riscv/helper.h | 95 ++ target/riscv/insn32.decode | 58 ++ target/riscv/insn_trans/trans_rvv.c.inc | 174 ++-- target/riscv/insn_trans/trans_rvvk.c.inc | 593 ++++++++++++ target/riscv/meson.build | 4 +- target/riscv/op_helper.c | 6 + target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 1052 ++++++++++++++++++++++ target/riscv/vector_helper.c | 243 +---- target/riscv/vector_internals.c | 81 ++ target/riscv/vector_internals.h | 228 +++++ tcg/tcg-op-gvec.c | 23 + 22 files changed, 2365 insertions(+), 363 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc create mode 100644 target/riscv/vcrypto_helper.c create mode 100644 target/riscv/vector_internals.c create mode 100644 target/riscv/vector_internals.h