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Mon, 27 Feb 2023 02:13:36 -0800 (PST) X-Google-Smtp-Source: AK7set/SaD/dW8i+ojgx6ctoZEQxoY5oUFivKhxTppWKAWemDMqh/2INQL+6ujJQ97IeAEqNAsYs+A== X-Received: by 2002:a17:907:1b08:b0:900:a150:cea4 with SMTP id mp8-20020a1709071b0800b00900a150cea4mr1539291ejc.37.1677492815950; Mon, 27 Feb 2023 02:13:35 -0800 (PST) Received: from avogadro.local ([2001:b07:6468:f312:63a7:c72e:ea0e:6045]) by smtp.gmail.com with ESMTPSA id q20-20020a1709060e5400b008e772c97db6sm2984777eji.128.2023.02.27.02.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 02:13:35 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: lei4.wang@intel.com, robert.hu@linux.intel.com, xiaoyao.li@intel.com, chenyi.qiang@intel.com Subject: [PATCH v4 0/4] target/i386: Add new CPU model SapphireRapids and new fast string op leaves Date: Mon, 27 Feb 2023 11:13:27 +0100 Message-Id: <20230227101332.636203-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sapphire Rapids enablement patches got stuck on the doubts regarding properties for AMX support. However, for now there is no need to have anything but hardcoded values, because all Intel processors with AMX currently support exactly the same palettes and TMUL limits. Intel has also promised that palette formats will remain backwards compatible so the only worry is for the TMUL leaf, CPUID[1Eh]. However, providing modifiable properties for AMX is premature. Rather, the first step should be to _validate_ host CPUID values against the ones supported by QEMU. So for now apply the simpler patch that only adds the new model. In addition, add the FZRM, FSRS, FSRC bits: first, they are now supported by Linux (albeit only in the upcoming 6.3 release); second, they are just markers that do not require any support in the hypervisors. While at it, this series also adds these new markers as well as FSRM to TCG's "-cpu max" model. Supersedes: <20230106083826.5384-1-lei4.wang@intel.com> Paolo Bonzini (3): target/i386: add FSRM to TCG target/i386: add FZRM, FSRS, FSRC target/i386: KVM: allow fast string operations if host supports them Wang, Lei (1): target/i386: Add new CPU model SapphireRapids target/i386/cpu.c | 142 ++++++++++++++++++++++++++++++++++++++++-- target/i386/cpu.h | 11 ++++ target/i386/kvm/kvm.c | 17 ++++- 3 files changed, 163 insertions(+), 7 deletions(-) Reviewed-by: Xiaoyao Li