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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id h4-20020a4a9404000000b004a532a32408sm8946830ooi.16.2023.01.12.14.34.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 14:34:50 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v6 0/2] hw/riscv: consolidate kernel init in riscv_load_kernel() Date: Thu, 12 Jan 2023 19:34:42 -0300 Message-Id: <20230112223444.484879-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c44; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc44.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hi, These are the 2 remaining patches, patches 10 and 11, of: "[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups" The first 9 patches are already available in riscv-to-apply.next. The only change made was in patch 10 where we're now handling the case where load_elf_ram_sym is padding the resulting kernel_entry with 1s for 32 bits. Patch 11 is unchanged. Changes from v5: - former patches 1-9: already pushed to riscv-to-apply.next - patch 10: - added an 'is_32bit' flag in riscv_load_kernel(). Use it to eliminate the sign-extension from load_elf() if we're running a 32-bit guest. v5 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg00051.html Daniel Henrique Barboza (2): hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv/boot.c | 98 ++++++++++++++++++++++++-------------- hw/riscv/microchip_pfsoc.c | 12 +---- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 13 ++--- hw/riscv/spike.c | 10 +--- hw/riscv/virt.c | 13 ++--- include/hw/riscv/boot.h | 3 +- 8 files changed, 77 insertions(+), 79 deletions(-)