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[98.35.17.78]) by smtp.gmail.com with ESMTPSA id q9-20020a170902bd8900b0016f035dcd75sm7505507pls.193.2022.08.29.07.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 07:23:30 -0700 (PDT) From: Ricky Zhou To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, Ricky Zhou Subject: [PATCH 0/1] target/i386: Raise #GP on unaligned m128 accesses when required. Date: Mon, 29 Aug 2022 07:23:25 -0700 Message-Id: <20220829142326.39562-1-ricky@rzhou.org> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=ricky.zhou@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 29 Aug 2022 10:59:21 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is a change to raise #GP on unaligned m128 loads/stores when required by the spec. Some notes on this change: 1. I considered making use of the existing support for enforcing memory alignment (setting MO_ALIGN_16 in the load/store's MemOp), but rejected this approach. There are at least two scenarios where we might want to do alignment checks in x86: a. Loads/stores when the AC flag is enabled (which should raise #AC on misalignment) b. SSE/AVX instructions which require memory alignment (which raise #GP on misalignment) The MemOp alignment checking mechanism can only handle one of these scenarios, since they require different exceptions to be raised. I think it make more sense to use the existing memory alignment support for implementing (a), since helper_unaligned_{ld,st} is already triggers SIGBUS in qemu-user. This is why I ended up implementing (b) with a helper. 2. It is often the case that legacy SSE instructions require 16 byte alignment of 128-bit memory operands, but AVX versions of the instructions do not (e.g. movsldup requires alignment and vmovsldup does not). From what I can tell, QEMU currently doesn't appear to report AVX support in cpuid, but it still seems to emulate some of these instructions if you tell it to execute them. This change attempts to distinguish between legacy SSE instructions and AVX instructions by by conditioning on !(s->prefix & PREFIX_VEX). Not sure this is very future-proof though - for example, it may need to be updated if support for EVEX prefixes is added. LMK if there's a nicer way to do this. 3. I tested this by running a Linux VM in qemu-system-x86_64 and verifying that movaps on an misaligned address triggers a segfault. Ricky Zhou (1): target/i386: Raise #GP on unaligned m128 accesses when required. target/i386/helper.h | 1 + target/i386/tcg/mem_helper.c | 8 ++++++++ target/i386/tcg/translate.c | 38 +++++++++++++++++++++++++++++++++--- 3 files changed, 44 insertions(+), 3 deletions(-)