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([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 00/17] accel/tcg + target/arm: pc-relative translation Date: Mon, 22 Aug 2022 16:23:21 -0700 Message-Id: <20220822232338.1727934-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Based-on: 20220819032615.884847-1-richard.henderson@linaro.org ("[PATCH v6 00/21] linux-user: Fix siginfo_t contents when jumping to non-readable pages") v1: https://lore.kernel.org/qemu-devel/20220816203400.161187-1-richard.henderson@linaro.org/ Just a simple refresh from v2 for the dependencies. r~ Richard Henderson (17): accel/tcg: Remove PageDesc code_bitmap accel/tcg: Use bool for page_find_alloc accel/tcg: Use DisasContextBase in plugin_gen_tb_start accel/tcg: Do not align tb->page_addr[0] include/hw/core: Create struct CPUJumpCache accel/tcg: Introduce tb_pc and tb_pc_log accel/tcg: Introduce TARGET_TB_PCREL accel/tcg: Split log_cpu_exec into inline and slow path target/arm: Introduce curr_insn_len target/arm: Change gen_goto_tb to work on displacements target/arm: Change gen_*set_pc_im to gen_*update_pc target/arm: Change gen_exception_insn* to work on displacements target/arm: Change gen_exception_internal to work on displacements target/arm: Change gen_jmp* to work on displacements target/arm: Introduce gen_pc_plus_diff for aarch64 target/arm: Introduce gen_pc_plus_diff for aarch32 target/arm: Enable TARGET_TB_PCREL include/exec/cpu-defs.h | 3 + include/exec/exec-all.h | 51 +++++- include/exec/plugin-gen.h | 7 +- include/hw/core/cpu.h | 9 +- target/arm/cpu-param.h | 2 + target/arm/translate-a32.h | 2 +- target/arm/translate.h | 21 ++- accel/tcg/cpu-exec.c | 108 +++++++---- accel/tcg/cputlb.c | 5 +- accel/tcg/plugin-gen.c | 23 +-- accel/tcg/translate-all.c | 168 ++++++----------- accel/tcg/translator.c | 2 +- target/arm/cpu.c | 23 +-- target/arm/translate-a64.c | 174 +++++++++++------- target/arm/translate-m-nocp.c | 6 +- target/arm/translate-mve.c | 2 +- target/arm/translate-vfp.c | 10 +- target/arm/translate.c | 232 +++++++++++++++--------- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 4 +- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/tcg/exception.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 4 +- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 4 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- tcg/tcg.c | 6 +- 33 files changed, 517 insertions(+), 371 deletions(-)