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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 21sm8870774wmk.45.2022.01.22.10.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Jan 2022 10:24:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 00/14] arm_gicv3_its: Implement MOVI and MOVALL commands Date: Sat, 22 Jan 2022 18:24:30 +0000 Message-Id: <20220122182444.724087-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shashi Mallela , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" I noticed while working on the new-in-GICv4 ITS commands that we'd forgotten to implement the GICv3 MOVI and MOVALL commands. These move interrupts from one redistributor to another; Linux doesn't use MOVALL but does use MOVI if it wants to power down a CPU (when it needs to migrate interrupts formerly targeting that CPU to a different one). This patchseries starts with a couple of patches that I found useful to improve the debug logging when I was writing this. It then has a collection of fixes for various minor bugs that I noticed while I was in the code (including yet another fix to the table lookup bounds checking...). Finally the last two patches implement the two new commands. thanks -- PMM Peter Maydell (14): target/arm: Log CPU index in 'Taking exception' log hw/intc/arm_gicv3_its: Add tracepoints hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs hw/intc/arm_gicv3_its: Sort ITS command list into numeric order hw/intc/arm_gicv3_redist: Remove unnecessary zero checks hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported hw/intc/arm_gicv3_its: Provide read accessor for translation_ops hw/intc/arm_gicv3_its: Make GITS_BASER RAZ/WI for unimplemented registers hw/intc/arm_gicv3_its: Check table bounds against correct limit hw/intc/arm_gicv3_its: Implement MOVALL hw/intc/arm_gicv3_its: Implement MOVI hw/intc/gicv3_internal.h | 43 ++++- include/hw/intc/arm_gicv3_its_common.h | 1 - target/arm/internals.h | 2 +- hw/intc/arm_gicv3.c | 1 + hw/intc/arm_gicv3_common.c | 9 + hw/intc/arm_gicv3_its.c | 258 +++++++++++++++++++++++-- hw/intc/arm_gicv3_redist.c | 115 ++++++++++- target/arm/helper.c | 9 +- target/arm/m_helper.c | 2 +- hw/intc/trace-events | 8 + 10 files changed, 416 insertions(+), 32 deletions(-)