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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id c12sm8286136pfm.113.2022.01.17.17.45.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:45:26 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions Date: Tue, 18 Jan 2022 09:45:03 +0800 Message-Id: <20220118014522.13613-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::633 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang In RVV v1.0 spec, several Zve* vector extensions for embedded processors are defined in Chapter 18.2: https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors This patchset implements Zve32f and Zve64f extensions. The port is available at: https://github.com/sifive/qemu/tree/rvv-zve32f-zve64f-upstream-v2 Zve32f can be enabled with -cpu option: Zve32f=true and Zve64f can be enabled with -cpu option: Zve64f=true. V is not required to be enabled explicitly. Here's the inclusion diagram for the six standard vector extensions quoted from Nick Knight : V | Zve64d | Zve64f / \ Zve64x Zve32f \ / Zve32x Changelog: v2: * Replace hardcoded TARGET_RISCV32 macro with get_xl(). Frank Chang (17): target/riscv: rvv-1.0: Add Zve64f extension into RISC-V target/riscv: rvv-1.0: Add Zve64f support for configuration insns target/riscv: rvv-1.0: Add Zve64f support for load and store insns target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns target/riscv: rvv-1.0: Allow Zve64f extension to be turned on target/riscv: rvv-1.0: Add Zve32f extension into RISC-V target/riscv: rvv-1.0: Add Zve32f support for configuration insns target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns target/riscv: rvv-1.0: Allow Zve32f extension to be turned on target/riscv/cpu.c | 6 + target/riscv/cpu.h | 2 + target/riscv/cpu_helper.c | 5 +- target/riscv/csr.c | 6 +- target/riscv/insn_trans/trans_rvv.c.inc | 219 ++++++++++++++++++++---- target/riscv/translate.c | 4 + 6 files changed, 205 insertions(+), 37 deletions(-) --- 2.31.1