mbox series

[v2,0/2] Align SiFive PDMA behavior to real hardware

Message ID 20220104063408.658169-1-jim.shu@sifive.com
Headers show
Series Align SiFive PDMA behavior to real hardware | expand

Message

Jim Shu Jan. 4, 2022, 6:34 a.m. UTC 
HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit
register, but QEMU emulation supports low part access now. Enhance QEMU
emulation to support high 32-bit access. 

Also, permit 4/8-byte valid access in PDMA as we have verified 32/64-bit
accesses of PDMA registers are supported.

Changelog:

v2:
  * Fix high 32-bit write access of 64-bit RO registers
  * Fix commit log

Jim Shu (2):
  hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
  hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers

 hw/dma/sifive_pdma.c | 181 +++++++++++++++++++++++++++++++++++++------
 1 file changed, 159 insertions(+), 22 deletions(-)

Comments

Alistair Francis Jan. 4, 2022, 9:54 p.m. UTC | #1 
On Tue, Jan 4, 2022 at 4:56 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit
> register, but QEMU emulation supports low part access now. Enhance QEMU
> emulation to support high 32-bit access.
>
> Also, permit 4/8-byte valid access in PDMA as we have verified 32/64-bit
> accesses of PDMA registers are supported.
>
> Changelog:
>
> v2:
>   * Fix high 32-bit write access of 64-bit RO registers
>   * Fix commit log
>
> Jim Shu (2):
>   hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
>   hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/dma/sifive_pdma.c | 181 +++++++++++++++++++++++++++++++++++++------
>  1 file changed, 159 insertions(+), 22 deletions(-)
>
> --
> 2.25.1
>
>