From patchwork Thu Aug 5 02:52:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 1513706 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GgCsW5wc9z9s1l for ; Thu, 5 Aug 2021 12:55:42 +1000 (AEST) Received: from localhost ([::1]:57208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTXl-00043W-H1 for incoming@patchwork.ozlabs.org; Wed, 04 Aug 2021 22:55:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTXP-00043D-29; Wed, 04 Aug 2021 22:55:16 -0400 Received: from out28-147.mail.aliyun.com ([115.124.28.147]:49862) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTXL-0004zf-TS; Wed, 04 Aug 2021 22:55:14 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.2728854|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0104754-0.000411257-0.989113; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047206; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvY9egp_1628132099; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvY9egp_1628132099) by smtp.aliyun-inc.com(10.147.41.121); Thu, 05 Aug 2021 10:55:00 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 00/13] Support UXL field in mstatus Date: Thu, 5 Aug 2021 10:52:59 +0800 Message-Id: <20210805025312.15720-1-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 Received-SPF: none client-ip=115.124.28.147; envelope-from=zhiwei_liu@c-sky.com; helo=out28-147.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This patch set implements UXL field in mstatus register. Programmer can change UXLEN by writting to this field. So that you can run a 32 bit program on a 64 bit CPU. This patch set depends on one patch set by Richard Henderson https://lists.gnu.org/archive/html/qemu-riscv/2021-07/msg00059.html. LIU Zhiwei (13): target/riscv: Add UXL to tb flags target/riscv: Support UXL32 for branch instructions target/riscv: Support UXL32 on 64-bit cpu for load/store target/riscv: Support UXL32 for slit/sltiu target/riscv: Support UXL32 for shift instruction target/riscv: Fix div instructions target/riscv: Support UXL32 for RVM target/riscv: Support UXL32 for vector instructions target/riscv: Support UXL32 for atomic instructions target/riscv: Support UXL32 for float instructions target/riscv: Fix srow target/riscv: Support UXL32 for RVB target/riscv: Changing the width of U-mode CSR target/riscv/cpu.h | 18 +++ target/riscv/csr.c | 42 +++++- target/riscv/insn_trans/trans_rva.c.inc | 36 ++++- target/riscv/insn_trans/trans_rvb.c.inc | 51 +++++-- target/riscv/insn_trans/trans_rvd.c.inc | 4 +- target/riscv/insn_trans/trans_rvf.c.inc | 4 +- target/riscv/insn_trans/trans_rvi.c.inc | 62 ++++++-- target/riscv/insn_trans/trans_rvm.c.inc | 24 ++- target/riscv/insn_trans/trans_rvv.c.inc | 44 +++--- target/riscv/translate.c | 186 ++++++++++++++++++++---- target/riscv/vector_helper.c | 54 +++++-- 11 files changed, 414 insertions(+), 111 deletions(-)