mbox series

[v5,0/4] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE

Message ID 20210317233301.4130-1-rebecca@nuviainc.com
Headers show
Series target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE | expand

Message

Rebecca Cran March 17, 2021, 11:32 p.m. UTC 
ARMv8.4 adds the mandatory FEAT_TLBIOS and FEAT_TLBIRANGE. 
They provides TLBI maintenance instructions that extend to the Outer
Shareable domain and that apply to a range of input addresses.

Changes from v4 to v5:

o Split changes to cputlb.c and exec_all.c into a separate commit.
o Return a bool from tlb_flush_page_bits_locked to indicate if a full
 flush has been done.
o Update flush_page_range_bits_* to exit early when a full flush has
 been done.
o Run tb_flush_jmp_cache in a separate loop.
o Don't check for 2 regimes for cases where we know there's only one.


Rebecca Cran (4):
  accel/tcg: Add TLB invalidation support for ranges of addresses
  target/arm: Add support for FEAT_TLBIRANGE
  target/arm: Add support for FEAT_TLBIOS
  target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type

 accel/tcg/cputlb.c      | 130 ++++++-
 include/exec/exec-all.h |  45 +++
 target/arm/cpu.h        |  10 +
 target/arm/cpu64.c      |   1 +
 target/arm/helper.c     | 369 ++++++++++++++++++++
 5 files changed, 552 insertions(+), 3 deletions(-)

Comments

no-reply@patchew.org March 17, 2021, 11:42 p.m. UTC | #1 
Patchew URL: https://patchew.org/QEMU/20210317233301.4130-1-rebecca@nuviainc.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210317233301.4130-1-rebecca@nuviainc.com
Subject: [PATCH v5 0/4] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20210317233301.4130-1-rebecca@nuviainc.com -> patchew/20210317233301.4130-1-rebecca@nuviainc.com
Switched to a new branch 'test'
39b3c36 target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
e3bc253 target/arm: Add support for FEAT_TLBIOS
94e5cc1 target/arm: Add support for FEAT_TLBIRANGE
85f8baf accel/tcg: Add TLB invalidation support for ranges of addresses

=== OUTPUT BEGIN ===
1/4 Checking commit 85f8baff74da (accel/tcg: Add TLB invalidation support for ranges of addresses)
WARNING: line over 80 characters
#238: FILE: include/exec/exec-all.h:354:
+static inline void tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,

WARNING: line over 80 characters
#239: FILE: include/exec/exec-all.h:355:
+                                                                       target_ulong addr,

ERROR: line over 90 characters
#240: FILE: include/exec/exec-all.h:356:
+                                                                       target_ulong length,

WARNING: line over 80 characters
#241: FILE: include/exec/exec-all.h:357:
+                                                                       uint16_t idxmap,

WARNING: line over 80 characters
#242: FILE: include/exec/exec-all.h:358:
+                                                                       unsigned bits)

total: 1 errors, 4 warnings, 217 lines checked

Patch 1/4 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

2/4 Checking commit 94e5cc1394b4 (target/arm: Add support for FEAT_TLBIRANGE)
3/4 Checking commit e3bc253926cd (target/arm: Add support for FEAT_TLBIOS)
4/4 Checking commit 39b3c36068b4 (target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210317233301.4130-1-rebecca@nuviainc.com/testing.checkpatch/?type=message.
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