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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id e12sm2795661pjj.23.2021.02.24.04.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Feb 2021 04:50:38 -0800 (PST) From: Bin Meng To: Alistair Francis , "Edgar E . Iglesias" , Peter Maydell Subject: [PATCH v5 0/5] hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI Date: Wed, 24 Feb 2021 20:50:19 +0800 Message-Id: <20210224125024.4160-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Francisco Iglesias , qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng ZynqMP QSPI supports SPI transfer using DMA mode, but currently this is unimplemented. When QSPI is programmed to use DMA mode, QEMU will crash. This is observed when testing VxWorks 7. We added a Xilinx CSU DMA model and the implementation is based on https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c and the one in Edgar's branch. The DST part of the model is verified along with ZynqMP GQSPI model. Changes in v5: - int_enable and int_disable do not affect each other - do not modify int_status int_disable_pre_write - set MEM_DONE in xlnx_csu_dma_done if it's SRC Changes in v4: - Add complete CSU DMA model based on Edgar's branch - Differences with Edgar's branch: 1. Match the registers' FIELD to UG1807. 2. Remove "byte-align" property. Per UG1807, SIZE and ADDR registers must be word aligned. 3. Make the values of int_enable and int_disable mutually exclusive otherwise IRQ cannot be delivered. 4. Clear int_status after int_disable is set. 5. Coding convention issues clean-up - remove one change that is not a checkpatch warning - Rename "csu_dma" to "qspi_dma" - Modify XLNX_ZYNQMP_SPIPS_R_MAX Changes in v3: - Implement DMA as a separate CSU DMA model - new patch: xlnx-zynqmp: Add XLNX CSU DMA module - new patch: xilinx_spips: Remove DMA related code from zynqmp_qspips Changes in v2: - Remove unconnected TYPE_STREAM_SINK link property - Add a TYPE_MEMORY_REGION link property, to allow board codes to tell the device what its view of the world that it is doing DMA to is - Replace cpu_physical_memory_write() with address_space_write() Xuzhou Cheng (5): hw/dma: xlnx_csu_dma: Implement a Xilinx CSU DMA model hw/arm: xlnx-zynqmp: Clean up coding convention issues hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI hw/ssi: xilinx_spips: Clean up coding convention issues hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips include/hw/arm/xlnx-zynqmp.h | 5 +- include/hw/dma/xlnx_csu_dma.h | 52 +++ include/hw/ssi/xilinx_spips.h | 2 +- hw/arm/xlnx-zynqmp.c | 21 +- hw/dma/xlnx_csu_dma.c | 741 ++++++++++++++++++++++++++++++++++ hw/ssi/xilinx_spips.c | 33 +- hw/arm/Kconfig | 1 + hw/dma/Kconfig | 4 + hw/dma/meson.build | 1 + 9 files changed, 836 insertions(+), 24 deletions(-) create mode 100644 include/hw/dma/xlnx_csu_dma.h create mode 100644 hw/dma/xlnx_csu_dma.c