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[83.53.161.74]) by smtp.gmail.com with ESMTPSA id z67sm464787wme.41.2020.09.28.10.15.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2020 10:15:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 00/16] hw/mips: Set CPU frequency Date: Mon, 28 Sep 2020 19:15:23 +0200 Message-Id: <20200928171539.788309-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.199, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Huacai Chen , Aleksandar Rikalo , Eduardo Habkost , Paul Burton , "Edgar E . Iglesias" , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Wainer dos Santos Moschetta , Aleksandar Markovic , =?utf-8?q?Herv=C3=A9?= =?utf-8?q?_Poussineau?= , Cleber Rosa , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" All the MIPS cores emulated by QEMU provides the Coproc#0 'Count' register which can be used as a free running timer. Since it's introduction in 2005 this timer uses a fixed frequency of 100 MHz (for a CPU freq of 200 MHz). While this is not an issue with Linux guests, it makes some firmwares behave incorrectly. The Clock API allow propagating clocks. It is particularly useful when hardware dynamicly changes clock frequencies. To be able to model such MIPS hardware, we need to refactor the MIPS hardware code to handle clocks. This series is organized as follow: - let all CPU have an input clock, - MIPS CPU get an input clock - when the clock is changed, CP0 timer is updated - set correct CPU frequencies to all boards - do not allow MIPS CPU without input clock I used a MIPSsim test suggested by Thomas. It is also included as bonus at the end. Possible follow up: - QOM'ify the GIC - let the GIC handle dynamic clock changes Regards, Phil. Philippe Mathieu-Daudé (16): hw/core/cpu: Let CPU object have a clock source target/mips: Move cpu_mips_get_random() with CP0 helpers target/mips/cp0_timer: Explicit unit in variable name target/mips/cpu: Introduce mips_cpu_properties[] target/mips/cpu: Set default CPU frequency to 200 MHz target/mips: Keep CP0 counter in sync with the CPU frequency hw/mips/r4k: Explicit CPU frequency is 200 MHz hw/mips/fuloong2e: Set CPU frequency to 533 MHz hw/mips/mipssim: Correct CPU frequency hw/mips/jazz: Correct CPU frequencies hw/mips/cps: Expose input clock and connect it to CPU cores hw/mips/boston: Set CPU frequency to 1 GHz hw/mips/malta: Set CPU frequency to 320 MHz hw/mips/cps: Do not allow use without input clock target/mips/cpu: Do not allow system-mode use without input clock tests/acceptance: Test the MIPSsim machine include/hw/core/cpu.h | 5 +++ include/hw/mips/cps.h | 2 + target/mips/cpu.h | 9 ++++ target/mips/internal.h | 2 +- hw/core/cpu.c | 12 +++++ hw/mips/boston.c | 13 ++++++ hw/mips/cps.c | 8 ++++ hw/mips/fuloong2e.c | 8 +++- hw/mips/jazz.c | 16 ++++++- hw/mips/malta.c | 20 +++++++-- hw/mips/mipssim.c | 12 ++++- hw/mips/r4k.c | 8 +++- target/mips/cp0_helper.c | 25 +++++++++++ target/mips/cp0_timer.c | 51 ++++++--------------- target/mips/cpu.c | 43 +++++++++++++++++- MAINTAINERS | 1 + tests/acceptance/machine_mips_mipssim.py | 56 ++++++++++++++++++++++++ 17 files changed, 244 insertions(+), 47 deletions(-) create mode 100644 tests/acceptance/machine_mips_mipssim.py