| Message ID | 20200225031222.15434-1-richard.henderson@linaro.org |
|---|---|
| Headers | show |
| Series | target/arm: Misc cleanups surrounding TBI | expand |
On Tue, 25 Feb 2020 at 03:12, Richard Henderson <richard.henderson@linaro.org> wrote: > > We have a bug at present wherein we do not supply the memory tag to > the memory system, so that on fault FAR_ELx does not contain the > correct value. > > For system mode, we already handle ignoring TBI in get_phys_addr_lpae, > as long as we don't actually drop the tag during translation. > For user mode, we don't have that option, so for now we must simply > accept that we'll get the wrong value in the siginfo_t. Something weird happened to this series: it looks like the first 2 patches were sent as replies to the cover letter, but then patches 3-8 were all replies to patch 2: https://lists.gnu.org/archive/html/qemu-devel/2020-02/msg06699.html The result is that neither patches nor patchew think they got the entire series. Could you resend it, please? thanks -- PMM
We have a bug at present wherein we do not supply the memory tag to the memory system, so that on fault FAR_ELx does not contain the correct value. For system mode, we already handle ignoring TBI in get_phys_addr_lpae, as long as we don't actually drop the tag during translation. For user mode, we don't have that option, so for now we must simply accept that we'll get the wrong value in the siginfo_t. In the process of looking at all that I found: * Exception return was not applying TBI in copying ELR_ELx to PC, - Extracting the current mmu_idx can be improved, - Replicating the TBI bits can allow bit 55 to be used unconditionally, eliminating a test. * DC_ZVA was not handling TBI (now only for user-mode) - The helper need not have been in op_helper.c, - The helper could have better tcg markup. * TBI still applies when translation is disabled, and we weren't raising AddressSpace for bad physical addresses. * SVE hasn't been updated to handle TBI. I have done nothing about this for now. For the moment, system mode will work properly, while user-only will only work without tags. I'll have to touch the same places to add MTE support, so it'll get done shortly. r~ Richard Henderson (8): target/arm: Replicate TBI/TBID bits for single range regimes target/arm: Optimize cpu_mmu_index target/arm: Apply TBI to ESR_ELx in helper_exception_return target/arm: Move helper_dc_zva to helper-a64.c target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva target/arm: Clean address for DC ZVA target/arm: Check addresses for disabled regimes target/arm: Disable clean_data_tbi for system mode target/arm/cpu.h | 23 ++++---- target/arm/helper-a64.h | 1 + target/arm/helper.h | 1 - target/arm/helper-a64.c | 114 ++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 44 +++++++++++--- target/arm/op_helper.c | 93 ------------------------------ target/arm/translate-a64.c | 13 ++++- 7 files changed, 175 insertions(+), 114 deletions(-)