| Message ID | 20200201192916.31796-1-richard.henderson@linaro.org |
|---|---|
| Headers | show |
| Series | target/arm: Implement ARMv8.1-VHE | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Version 6 moves vhe_reginfo[] to file scope, and one tweak > to the vhe register access masking that Peter asked for. > > All patches now have reviews. I was re-testing and I was able to boot my guest Image+buildroot. However the busybox crashes after login so I'm unable to do stuff in the guests userspace. I seem to recall we saw this last time but I can't remember what the problem was. > > > r~ > > > Alex Bennée (1): > target/arm: check TGE and E2H flags for EL0 pauth traps > > Richard Henderson (40): > target/arm: Define isar_feature_aa64_vh > target/arm: Enable HCR_E2H for VHE > target/arm: Add CONTEXTIDR_EL2 > target/arm: Add TTBR1_EL2 > target/arm: Update CNTVCT_EL0 for VHE > target/arm: Split out vae1_tlbmask > target/arm: Split out alle1_tlbmask > target/arm: Simplify tlb_force_broadcast alternatives > target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* > target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 > target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* > target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] > target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 > target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 > target/arm: Recover 4 bits from TBFLAGs > target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits > target/arm: Rearrange ARMMMUIdxBit > target/arm: Tidy ARMMMUIdx m-profile definitions > target/arm: Reorganize ARMMMUIdx > target/arm: Add regime_has_2_ranges > target/arm: Update arm_mmu_idx for VHE > target/arm: Update arm_sctlr for VHE > target/arm: Update aa64_zva_access for EL2 > target/arm: Update ctr_el0_access for EL2 > target/arm: Add the hypervisor virtual counter > target/arm: Update timer access for VHE > target/arm: Update define_one_arm_cp_reg_with_opaque for VHE > target/arm: Add VHE system register redirection and aliasing > target/arm: Add VHE timer register redirection and aliasing > target/arm: Flush tlb for ASID changes in EL2&0 translation regime > target/arm: Flush tlbs for E2&0 translation regime > target/arm: Update arm_phys_excp_target_el for TGE > target/arm: Update {fp,sve}_exception_el for VHE > target/arm: Update get_a64_user_mem_index for VHE > target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE > target/arm: Enable ARMv8.1-VHE in -cpu max > target/arm: Move arm_excp_unmasked to cpu.c > target/arm: Pass more cpu state to arm_excp_unmasked > target/arm: Use bool for unmasked in arm_excp_unmasked > target/arm: Raise only one interrupt in arm_cpu_exec_interrupt > > target/arm/cpu-param.h | 2 +- > target/arm/cpu-qom.h | 1 + > target/arm/cpu.h | 423 +++++-------- > target/arm/internals.h | 73 ++- > target/arm/translate.h | 4 +- > target/arm/cpu.c | 162 ++++- > target/arm/cpu64.c | 1 + > target/arm/debug_helper.c | 50 +- > target/arm/helper-a64.c | 2 +- > target/arm/helper.c | 1220 +++++++++++++++++++++++++++--------- > target/arm/pauth_helper.c | 14 +- > target/arm/translate-a64.c | 47 +- > target/arm/translate.c | 74 ++- > 13 files changed, 1392 insertions(+), 681 deletions(-) -- Alex Bennée
On 2/3/20 5:51 PM, Alex Bennée wrote: > > Richard Henderson <richard.henderson@linaro.org> writes: > >> Version 6 moves vhe_reginfo[] to file scope, and one tweak >> to the vhe register access masking that Peter asked for. >> >> All patches now have reviews. > > I was re-testing and I was able to boot my guest Image+buildroot. > However the busybox crashes after login so I'm unable to do stuff in the > guests userspace. I seem to recall we saw this last time but I can't > remember what the problem was. Hmm. Mine works. Are you testing a 32-bit nested guest again? I've misplaced those images that you put together in December, so I can't test that in short order. r~
Alex Bennée <alex.bennee@linaro.org> writes: > Richard Henderson <richard.henderson@linaro.org> writes: > >> Version 6 moves vhe_reginfo[] to file scope, and one tweak >> to the vhe register access masking that Peter asked for. >> >> All patches now have reviews. > > I was re-testing and I was able to boot my guest Image+buildroot. > However the busybox crashes after login so I'm unable to do stuff in the > guests userspace. I seem to recall we saw this last time but I can't > remember what the problem was. PEBKAC I've now deleted the errant Image and re-tested with both 32 bit and 64 bit EL0 userspaces in the guest. So keep my: Tested-by: Alex Bennée <alex.bennee@linaro.org> > >> >> >> r~ >> >> >> Alex Bennée (1): >> target/arm: check TGE and E2H flags for EL0 pauth traps >> >> Richard Henderson (40): >> target/arm: Define isar_feature_aa64_vh >> target/arm: Enable HCR_E2H for VHE >> target/arm: Add CONTEXTIDR_EL2 >> target/arm: Add TTBR1_EL2 >> target/arm: Update CNTVCT_EL0 for VHE >> target/arm: Split out vae1_tlbmask >> target/arm: Split out alle1_tlbmask >> target/arm: Simplify tlb_force_broadcast alternatives >> target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* >> target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 >> target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* >> target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] >> target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 >> target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 >> target/arm: Recover 4 bits from TBFLAGs >> target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits >> target/arm: Rearrange ARMMMUIdxBit >> target/arm: Tidy ARMMMUIdx m-profile definitions >> target/arm: Reorganize ARMMMUIdx >> target/arm: Add regime_has_2_ranges >> target/arm: Update arm_mmu_idx for VHE >> target/arm: Update arm_sctlr for VHE >> target/arm: Update aa64_zva_access for EL2 >> target/arm: Update ctr_el0_access for EL2 >> target/arm: Add the hypervisor virtual counter >> target/arm: Update timer access for VHE >> target/arm: Update define_one_arm_cp_reg_with_opaque for VHE >> target/arm: Add VHE system register redirection and aliasing >> target/arm: Add VHE timer register redirection and aliasing >> target/arm: Flush tlb for ASID changes in EL2&0 translation regime >> target/arm: Flush tlbs for E2&0 translation regime >> target/arm: Update arm_phys_excp_target_el for TGE >> target/arm: Update {fp,sve}_exception_el for VHE >> target/arm: Update get_a64_user_mem_index for VHE >> target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE >> target/arm: Enable ARMv8.1-VHE in -cpu max >> target/arm: Move arm_excp_unmasked to cpu.c >> target/arm: Pass more cpu state to arm_excp_unmasked >> target/arm: Use bool for unmasked in arm_excp_unmasked >> target/arm: Raise only one interrupt in arm_cpu_exec_interrupt >> >> target/arm/cpu-param.h | 2 +- >> target/arm/cpu-qom.h | 1 + >> target/arm/cpu.h | 423 +++++-------- >> target/arm/internals.h | 73 ++- >> target/arm/translate.h | 4 +- >> target/arm/cpu.c | 162 ++++- >> target/arm/cpu64.c | 1 + >> target/arm/debug_helper.c | 50 +- >> target/arm/helper-a64.c | 2 +- >> target/arm/helper.c | 1220 +++++++++++++++++++++++++++--------- >> target/arm/pauth_helper.c | 14 +- >> target/arm/translate-a64.c | 47 +- >> target/arm/translate.c | 74 ++- >> 13 files changed, 1392 insertions(+), 681 deletions(-)
Version 6 moves vhe_reginfo[] to file scope, and one tweak to the vhe register access masking that Peter asked for. All patches now have reviews. r~ Alex Bennée (1): target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson (40): target/arm: Define isar_feature_aa64_vh target/arm: Enable HCR_E2H for VHE target/arm: Add CONTEXTIDR_EL2 target/arm: Add TTBR1_EL2 target/arm: Update CNTVCT_EL0 for VHE target/arm: Split out vae1_tlbmask target/arm: Split out alle1_tlbmask target/arm: Simplify tlb_force_broadcast alternatives target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 target/arm: Recover 4 bits from TBFLAGs target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits target/arm: Rearrange ARMMMUIdxBit target/arm: Tidy ARMMMUIdx m-profile definitions target/arm: Reorganize ARMMMUIdx target/arm: Add regime_has_2_ranges target/arm: Update arm_mmu_idx for VHE target/arm: Update arm_sctlr for VHE target/arm: Update aa64_zva_access for EL2 target/arm: Update ctr_el0_access for EL2 target/arm: Add the hypervisor virtual counter target/arm: Update timer access for VHE target/arm: Update define_one_arm_cp_reg_with_opaque for VHE target/arm: Add VHE system register redirection and aliasing target/arm: Add VHE timer register redirection and aliasing target/arm: Flush tlb for ASID changes in EL2&0 translation regime target/arm: Flush tlbs for E2&0 translation regime target/arm: Update arm_phys_excp_target_el for TGE target/arm: Update {fp,sve}_exception_el for VHE target/arm: Update get_a64_user_mem_index for VHE target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE target/arm: Enable ARMv8.1-VHE in -cpu max target/arm: Move arm_excp_unmasked to cpu.c target/arm: Pass more cpu state to arm_excp_unmasked target/arm: Use bool for unmasked in arm_excp_unmasked target/arm: Raise only one interrupt in arm_cpu_exec_interrupt target/arm/cpu-param.h | 2 +- target/arm/cpu-qom.h | 1 + target/arm/cpu.h | 423 +++++-------- target/arm/internals.h | 73 ++- target/arm/translate.h | 4 +- target/arm/cpu.c | 162 ++++- target/arm/cpu64.c | 1 + target/arm/debug_helper.c | 50 +- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 1220 +++++++++++++++++++++++++++--------- target/arm/pauth_helper.c | 14 +- target/arm/translate-a64.c | 47 +- target/arm/translate.c | 74 ++- 13 files changed, 1392 insertions(+), 681 deletions(-)