From patchwork Thu Mar 7 18:05:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1053205 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44FfdK6gn5z9s9N for ; Fri, 8 Mar 2019 05:42:45 +1100 (AEDT) Received: from localhost ([127.0.0.1]:57191 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1xyd-0004U3-TI for incoming@patchwork.ozlabs.org; Thu, 07 Mar 2019 13:42:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48289) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1xOf-00078d-It for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1xOe-0006E0-28 for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:33 -0500 Received: from [2001:41c9:1:41f::167] (port=51946 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1xOb-00069i-GZ; Thu, 07 Mar 2019 13:05:29 -0500 Received: from host86-177-156-179.range86-177.btcentralplus.com ([86.177.156.179] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h1xOW-0000Tl-4D; Thu, 07 Mar 2019 18:05:24 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Thu, 7 Mar 2019 18:05:13 +0000 Message-Id: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 X-SA-Exim-Connect-IP: 86.177.156.179 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH v2 0/7] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" After some investigation into Andrew's report of corruption in his ppc64le tests at https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg07234.html, I discovered the underlying cause was that the first 32 VSX registers are not stored in host endian order. This is something that Richard and I had discussed before, but missed that with VSX if you have source registers from different register sets then even logical operations will give you the wrong result. Rather than revert 7b8fe477e1 "target/ppc: convert VSX logical operations to vector operations" let's keep the use of the accelerated vector instructions, and instead fix the real problem which is to switch the first 32 VSX registers to host endian order matching the VMX registers. Patches 1-5 aim to consolidate the offset calculations for both CPUPPCState and the associated _ptr() functions into one single place. With this preliminary work complete, patch 6 switches the first 32 registers into host endian order without too much difficulty. Finally now that all VSX registers are stored in the same way, the vsr offset functions and get_cpu_vsrh()/get_cpu_vsrl() can be simplified accordingly. Signed-off-by: Mark Cave-Ayland v2: - Rebase onto master - Rework patchset set based upon av64_offset()/vsr64_offset() as suggested by Richard, rather than using separate low/high accessors Mark Cave-Ayland (7): target/ppc: introduce single fpr_offset() function target/ppc: introduce single vsrl_offset() function target/ppc: move Vsr* macros from internal.h to cpu.h target/ppc: introduce avr_full_offset() function target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64() target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() target/ppc/cpu.h | 51 ++++++++++++++++++++++++++++++++++--- target/ppc/internal.h | 27 +++----------------- target/ppc/machine.c | 8 +++--- target/ppc/translate.c | 20 +++------------ target/ppc/translate/vmx-impl.inc.c | 27 ++++++++------------ target/ppc/translate/vsx-impl.inc.c | 39 +++------------------------- 6 files changed, 75 insertions(+), 97 deletions(-)