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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.39.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:39:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:51 -0800 Message-Id: <20190223023957.18865-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62f Subject: [Qemu-devel] [PATCH+RFC 0/6] target/arm: Define cortex-a{73, 75, 76} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" There have been several announcements since the a72. The a75 and a76 entries are RFC because, while they boot with a 3.15 kernel, they do not boot with a 5.0-rc7 kernel. I'm really not sure where things have gone off the rails. It'll take some more serious tracing to figure out what went wrong. I post this now mostly to get feedback on patch 5. Should we do more to elide *all* of the aa32 system registers for that case? r~ Richard Henderson (6): target/arm: Implement ID_PFR2 target/arm: Define cortex-a73 target/arm: Implement ID_AA64MMFR2 target/arm: Define cortex-a75 target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert target/arm: Define cortex-a76 target/arm/cpu.h | 18 +++++ hw/arm/virt.c | 3 + target/arm/cpu64.c | 179 +++++++++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 66 ++++++++++------ target/arm/kvm64.c | 2 + 5 files changed, 240 insertions(+), 28 deletions(-)